Design of 4 Bit Adder using Loops (Behavior Modeling Style) (verilog code)

Design of 4 Bit Adder using Loops (Behavior Modeling Style) -

Output Waveform :   4 Bit adder

Verilog CODE- 


//-----------------------------------------------------------------------------
//
// Title       : adder_4bit
// Design      : verilog upload 4
// Author      : Naresh Singh Dobal
// Company     : nsdobal@gmail.com
// Verilog Programs & Exercise with Naresh Singh Dobal
//
//-----------------------------------------------------------------------------
//
// File        : Design of 4 bit adder using loop.v


module adder_4bit ( a ,b ,sum ,carry );

output [3:0] sum ;
reg [3:0] sum ;
output carry ;
reg carry ;

input [3:0] a ;
wire [3:0] a ;
input [3:0] b ;
wire [3:0] b ;

integer i;

reg [4:0]s;

always @ (a or b) begin
s[0] = 0;
for (i=0;i<=3;i=i+1) begin
sum [i] = a[i] ^ b[i] ^ s[i];
s[i+1] = (a[i] & b[i]) | (b[i] & s[i]) | (s[i] & a[i]);
end
carry = s[4];
end

endmodule