Design of 8 Nibble ROM (Memory) using Behavior Modeling Style (Verilog CODE)-

Design of 8 Nibble ROM (Memory) using Behavior Modeling Style -

Output Waveform :  ROM (Memory) 8 nibble.

Verilog CODE -


//-----------------------------------------------------------------------------
//
// Title       : rom_memory
// Design      : verilog upload 4
// Author      : Naresh Singh Dobal
// Company     : nsdobal@gmail.com
// Verilog Programs & Exercise with Naresh Singh Dobal
//
//-----------------------------------------------------------------------------
//
// File        : Design of 8 nibble ROM (Memory) using Behavior Modeling Style (Verilog CODE).v


module rom_memory ( en ,addr ,dout );

output [3:0] dout ;
reg [3:0] dout ;

input en ;
wire en ;
input [2:0] addr ;
wire [2:0] addr ;

wire [3:0]mem[0:7];

assign mem[0] = 15;
assign mem[1] = 14;
assign mem[2] = 13;
assign mem[3] = 12;
assign mem[4] = 11;
assign mem[5] = 10;
assign mem[6] = 9;
assign mem[7] = 8;

always @ (en or addr) begin
if (en)
dout = mem[addr];
end


endmodule