tag:blogger.com,1999:blog-57875586070750388252024-02-06T20:40:40.364-08:00Verilog Programming By Naresh Singh DobalAnonymoushttp://www.blogger.com/profile/03989667403249817442noreply@blogger.comBlogger108125tag:blogger.com,1999:blog-5787558607075038825.post-50039371308685280482013-11-12T02:51:00.005-08:002013-11-12T02:51:50.332-08:00A Small Discussion about VHDL & Verilog HDL...<div dir="ltr" style="text-align: left;" trbidi="on">
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<span style="background-color: #fce5cd;"><span style="font-size: large;"><u><b>A Small Discussion about VHDL & Verilog HDL -</b></u></span></span><br />
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<tr><td><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhymwBKW27t1RJ4kIyQkkrgO0JJEj4UU27QGfbwrI11FTRAErDV1IHkH5oswzEnOMDGZEK35i4SgHLrC9EetuH_Bm60TRcLiEaAgc3wauDhYDym_UQoUrDwMgpQeum5H3bfAW6XSuN5C5D0/s1600/img11-12-2013-4.13.52+PM.jpg" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhymwBKW27t1RJ4kIyQkkrgO0JJEj4UU27QGfbwrI11FTRAErDV1IHkH5oswzEnOMDGZEK35i4SgHLrC9EetuH_Bm60TRcLiEaAgc3wauDhYDym_UQoUrDwMgpQeum5H3bfAW6XSuN5C5D0/s1600/img11-12-2013-4.13.52+PM.jpg" /></a></td></tr>
<tr><td class="tr-caption">VHDL or Verilog HDL - A small discussion (Verilog HDL with Naresh Singh Dobal learning Series).</td></tr>
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<span style="font-family: Arial,Helvetica,sans-serif;"><b>Verilog HDL is easier to understand and use, It is very effectively used for
simulation and synthesis. but it lacks for system level or complex designing.
It is promoted by OVI (Open Verilog International). It is widely used for ASIC
designing or lower level design (RTL or lower), but this results in
faster simulation and effective synthesis. Mostly used in North America, Asia
& Japan, but not popular in Europe.</b></span></div>
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<span style="font-family: Arial,Helvetica,sans-serif;"><b>As comparable to verilog HDL, VHDL is more complex, thus difficult to learn
and use. But this offers more flexibility of designing. Since VHDL is better
suited for handling very complex systems, so it is now gaining popularity. VHDL
is mainly promoted by VHDL
international. VHDL is relatively weaker in lower designs. But superior in
system level design. Many believes that in long terms presents better condition
and adaptability than its competitors. This language is widely used in Europe,
significantly used in US and Canada, but this disliked in Japan...</b></span></div>
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<span style="font-family: Arial,Helvetica,sans-serif;"><b>Both the HDL's are used to describe electronic systems.</b></span></div>
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<span style="font-family: Arial,Helvetica,sans-serif;"><b>The function of systems is to get input data from it's environment and give
output some data in return.</b></span></div>
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<span style="font-family: Arial,Helvetica,sans-serif;"><b>In verilog HDL this is called a module which is a basic building block in
Verilog HDL, and in VHDL this is defined in Entity & Architecture Pair.</b></span></div>
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<span style="font-family: Arial,Helvetica,sans-serif;"><b> Both the Languages are IEEE Standard.</b></span></div>
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<span style="font-family: Arial,Helvetica,sans-serif;"><b><br />
I would love to read your suggestions and comments here below,</b></span></div>
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<span style="font-family: Arial,Helvetica,sans-serif;"><b>Best Regard //</b></span></div>
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<span style="font-family: Arial,Helvetica,sans-serif;"><b>
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<span style="font-family: Arial,Helvetica,sans-serif;"><b>Naresh Singh Dobal</b></span></div>
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<span style="font-family: Arial,Helvetica,sans-serif;"><b>nsdobal@gmail.com</b></span></div>
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Anonymoushttp://www.blogger.com/profile/03989667403249817442noreply@blogger.com3tag:blogger.com,1999:blog-5787558607075038825.post-81479467140879006292013-11-11T00:56:00.000-08:002013-11-11T00:56:02.800-08:00Basics of Verilog HDL Language Execution Process (Concurrent and Sequential) -<div dir="ltr" style="text-align: left;" trbidi="on">
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<span style="background-color: #fce5cd;"><span style="font-size: large;"><u><b>Basics of Verilog HDL Language Executioin Process (Concurrent and Sequential). -</b></u></span></span><br />
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjRPeec7fz0QlfFiUXjtve8otIsbAvOXtMc2WLBfgDqyCtjIsxvVk9ofahE_QmIHo0ylmoIwlJxWyLycTooYyAmPDMwrITME-hWk036StwfjQOvaNZH1G-MQGAlCx4p_xcftLmWyfd48j0l/s1600/img11-11-2013-2.19.56+PM.jpg" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjRPeec7fz0QlfFiUXjtve8otIsbAvOXtMc2WLBfgDqyCtjIsxvVk9ofahE_QmIHo0ylmoIwlJxWyLycTooYyAmPDMwrITME-hWk036StwfjQOvaNZH1G-MQGAlCx4p_xcftLmWyfd48j0l/s1600/img11-11-2013-2.19.56+PM.jpg" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Basics of Verilog HDL Language Execution Process (Verilog HDL with Naresh Singh Dobal learning Series)</td><td class="tr-caption" style="text-align: center;"><br /></td></tr>
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<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt;">Hello
Friends,</span></b></div>
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</b><div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"><span style="mso-spacerun: yes;"> </span>Before start writing of codes in </span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Verilog</span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"> HDL for digital systems you must
know about the execution of </span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Verilg</span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"> HDL language,
you should know that how the tools process the </span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Verilog</span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"> HDL code. This is a very important concept you should
understand for proficiency in </span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Verilog</span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"> HDL.</span></b></div>
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</b><div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<span style="background-color: #fce5cd;"><b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Verilog</span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"> HDL can be programmed in following execution pattern.</span></b></span></div>
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<b><span style="font-size: 12.0pt;"><span style="mso-special-format: "numbullet3\,1";">1.</span></span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Concurrent Execution.</span></b></div>
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<b><span style="font-size: 12.0pt;"><span style="mso-special-format: "numbullet3\,1";">2.</span></span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Sequential Execution.</span></b></div>
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<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"> </span></b></div>
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<span style="background-color: #fce5cd;"><b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Verilog</span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"> HDL can work on –</span></b></span></div>
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<b><span style="font-size: 12.0pt;"><span style="mso-special-format: "numbullet3\,1";">1.</span></span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Concurrent Language.</span></b></div>
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<b><span style="font-size: 12.0pt;"><span style="mso-special-format: "numbullet3\,1";">2.</span></span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Sequential Language.</span></b></div>
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<b><span style="font-size: 12.0pt;"><span style="mso-special-format: "numbullet3\,1";">3.</span></span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Net-List Language.</span></b></div>
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<b><span style="font-size: 12.0pt;"><span style="mso-special-format: "numbullet3\,1";">4.</span></span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Timing Specification.</span></b></div>
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<b><span style="font-size: 12.0pt;"><span style="mso-special-format: "numbullet3\,1";">5.</span></span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Waveform Generation Language.</span></b></div>
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<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">
</span></b></div>
<b>
</b><div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-left: .25in; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; text-indent: -.25in; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Before describing all above language I want to ask a
question to you…….This will help you to understand the concept.</span></b></div>
<b>
</b><div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-left: .25in; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; text-indent: -.25in; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">My question is, -<span style="mso-spacerun: yes;">
</span>Suppose we have a real life IC and we are using that in a hardware
circuit and we have four inputs and four outputs in IC, so is it possible to
give inputs one by one I mean is it possible to give it input to first pin and
others are idle or after some time input switch to second pin. And so
on…………………. Is it ??????????</span></b></div>
<b>
</b><div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-left: .25in; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; text-indent: -.25in; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">
</span></b></div>
<b>
</b><div style="direction: ltr; language: en-US; line-height: normal; margin-bottom: 0pt; margin-left: .25in; margin-right: 0in; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; text-indent: -.25in; unicode-bidi: embed; vertical-align: baseline; word-break: normal;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Answer is No,
Obviously this is not possible in real life, If one IC having four inputs and
then we have to give all the inputs in same time, doesn’t matter our inputs are
affecting the outputs or not. But we have to give all the inputs to all pins at
a same time.</span></b></div>
<div style="direction: ltr; language: en-US; line-height: normal; margin-bottom: 0pt; margin-left: .25in; margin-right: 0in; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; text-indent: -.25in; unicode-bidi: embed; vertical-align: baseline; word-break: normal;">
<br /></div>
<b>
</b><div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-left: .25in; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; text-indent: -.25in; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">
</span></b></div>
<b>
</b><div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-left: .25in; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; text-indent: -.25in; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">That means we can easily say that all the real life IC
working on concurrent fashion. And all our HDL tools are also performs
concurrent execution to get real life working environment. And we have to
define all the connections of gates and Registers threw nets, or we must define
the flow of data from input to output. But in that manner we must know the
structure of hardware system. This is a very difficult task for designers for
complex system. As we know today we have multi-billion transistors in a single
IC chip, so this is practically impossible to design a complete system in term
of structure.<span style="mso-spacerun: yes;"> </span></span></b></div>
<div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-left: .25in; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; text-indent: -.25in; unicode-bidi: embed; vertical-align: baseline;">
<br /></div>
<div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-left: .25in; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; text-indent: -.25in; unicode-bidi: embed; vertical-align: baseline;">
<br /></div>
<div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-left: .25in; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; text-indent: -.25in; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"><span style="mso-spacerun: yes;">In solution of that probelm designer prefer Sequential Language. </span></span></b></div>
<b>
</b><div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">
</span></b></div>
<b>
</b><div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">
</span></b></div>
<b>
</b><div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<span style="background-color: #fce5cd;"><b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Next is Sequential Execution - </span></b></span></div>
<b>
</b><div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">I am going to start describing this
with the most widely used execution process which is used in multiple
languages. If we talk about software languages most of them are worked on
Sequential processing or line by line processing concept. VHDL or </span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Verilog</span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"> HDL both are working on Sequential
language as well. This makes our designing process very easy, because using of
different sequential concepts like if-else, case, loops, edge-triggering etc.
so now if we have to design a 4 bit comparator we just write<span style="mso-spacerun: yes;"> </span></span></b></div>
<div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<br /></div>
<b>
</b><div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">
</span></b></div>
<b>
</b><div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">
</span></b></div>
<b>
</b><div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">If (a=b) then</span></b></div>
<b>
</b><div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"><span style="mso-spacerun: yes;">
</span></span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">eq</span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"> <= ‘1’;</span></b></div>
<b>
</b><div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Else</span></b></div>
<b>
</b><div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"><span style="mso-spacerun: yes;">
</span></span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">eq</span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"> <= ‘0’;</span></b></div>
<b>
</b><div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">End if;</span></b></div>
<div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<br /></div>
<b>
</b><div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">
</span></b></div>
<b>
</b><div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">** where a and b are 4 bit inputs
and </span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">eq</span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"> is 1 bit output.</span></b></div>
<b>
</b><div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">
</span></b></div>
<b>
</b><div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">But my question to you is, how you
define a sequential language with a hardware part. Because in sequential
execution statements will perform according to line by line, and in hardware
all process should be taken at same time. So how we configure our system
(designed using sequential execution) in real life hardware……..???????</span></b></div>
<div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<br /></div>
<b>
</b><div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">
</span></b></div>
<b>
</b><div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<span style="background-color: #fce5cd;"><b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Let me explain –</span></b></span></div>
<b>
</b><div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Firt</span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"> you should
know what is configured in our hardware, We code our system in HDL (concurrent
+ sequential) but that </span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">hdl</span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"> code never
configured with hardware, what is configured – RTL, that means we have to
convert our HDL code into RTL structure before configuring. Which provide
physical connection of all physical registers. Registers which I have defined
in my previous post (individual basic gate or a combination of gates).</span></b></div>
<div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<br /></div>
<div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<br /></div>
<b>
</b><div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">
</span></b></div>
<b>
</b><div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12pt; vertical-align: baseline;">** Also remember
normally all our HDL's perform concurrent execution, If some one ask you that </span><span style="color: black; font-family: Arial; font-size: 12pt; vertical-align: baseline;">Verilog</span><span style="color: black; font-family: Arial; font-size: 12pt; vertical-align: baseline;"> HDL is basically what type of
language then answer is -</span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt;">
</span></b></div>
<b>
</b><div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12pt; vertical-align: baseline;">Verilog</span><span style="color: black; font-family: Arial; font-size: 12pt; vertical-align: baseline;"> HDL is Concurrent type of language,
but it supports Sequential language as well.</span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt;">
</span></b></div>
<b>
</b><div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12pt; vertical-align: baseline;">and If we need
sequential language anywhere then we convert our execution from concurrent to
sequential, later I will tell you how we convert the way of execution and what
keywords designers use for that purpose.</span></b></div>
<div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12pt; vertical-align: baseline;"> </span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt;">
</span></b></div>
<b>
</b><div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">
</span></b></div>
<b>
</b><div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">
</span></b></div>
<b>
</b><div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Now I believe that you understand
both the executions </span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">i.e</span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">, concurrent
or sequential.</span></b></div>
<div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<br /></div>
<div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<br /></div>
<b>
</b><div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">
</span></b></div>
<b>
</b><div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">
</span></b></div>
<b>
</b><div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<span style="background-color: #fce5cd;"><b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Net list language –</span></b></span></div>
<b>
</b><div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Net list language is also working on
Concurrent execution. But only the difference is in net list language we design
our system by defining the basic elements like gates or collection of gates
(called modules and registers). </span></b></div>
<div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<br /></div>
<b>
</b><div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">
</span></b></div>
<b>
</b><div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Above three languages are used for
designing purpose.</span></b></div>
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<b>
</b><div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">
</span></b></div>
<b>
</b><div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Other two languages i.e. Timing
specification and<span style="mso-spacerun: yes;"> </span>waveform generation
language are used for verification purpose. In brief -</span></b></div>
<div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<br /></div>
<b>
</b><div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"><span style="background-color: #fce5cd;">Timing Specification -</span><span style="mso-spacerun: yes;"> </span>we can define the flow of data from input to
output in our simulation screen but again this can not be implement in real
life hardware because you can't specify the time of flow of data. So timing
specification language only use in writing of test benches. Same a waveform
generation language, Is used for creation of waveforms,
basically this is a<span style="mso-spacerun: yes;"> </span>algorithm to get the
same output by minimizing the processing time.</span></b></div>
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<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"> </span></b></div>
<b>
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<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">
</span></b></div>
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<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">
</span></b></div>
<b>
</b><div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">
</span></b></div>
<b>
</b><div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">For more information you can go with
our video tutorial series.</span></b></div>
<b>
</b><div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">
</span></b></div>
<b>
</b><div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">I would love to read your comments
and suggestions in comment bar below…</span></b></div>
<b>
</b><div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">My name is “Naresh Singh Dobal”, for
any query you can write us directly at<span style="mso-spacerun: yes;">
</span>nsdobal@gmail.com</span></b></div>
<div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
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</span></div>
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</span></div>
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Anonymoushttp://www.blogger.com/profile/03989667403249817442noreply@blogger.com1tag:blogger.com,1999:blog-5787558607075038825.post-9645891019850264652013-11-08T01:57:00.003-08:002013-11-08T02:03:00.479-08:00Chip / FPGA Design Flow<div dir="ltr" style="text-align: left;" trbidi="on">
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<div style="direction: ltr; margin-bottom: 0pt; margin-top: 4.32pt; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<span style="background-color: #fce5cd;"><span style="font-family: Arial,Helvetica,sans-serif;"><span style="font-size: large;"><b><u><span style="color: black; font-weight: normal;"></span><span style="color: black; font-weight: normal; vertical-align: baseline;">FPGA </span><span style="color: black; font-weight: normal;">Design Flow –</span></u></b></span></span></span></div>
<div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
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<div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<span style="color: black; font-family: Arial; font-size: 12.0pt; font-weight: normal; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt;"> <table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEh69t3XTp-ECSwkUGeYxZB1iSdatSusfRxPT2B8o2-8E7rVk_ElUPJNAxx4c-XR2SrSHNwrUwxFgGI3uy0lcu4bl9Ez3cgQjEgFsVbk0T_rc7pqq_XBBS51GVgZ2K7e5AoHcya6naWWOMfY/s1600/img11-8-2013-3.19.35+PM.jpg" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEh69t3XTp-ECSwkUGeYxZB1iSdatSusfRxPT2B8o2-8E7rVk_ElUPJNAxx4c-XR2SrSHNwrUwxFgGI3uy0lcu4bl9Ez3cgQjEgFsVbk0T_rc7pqq_XBBS51GVgZ2K7e5AoHcya6naWWOMfY/s1600/img11-8-2013-3.19.35+PM.jpg" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">FPGA Design Flow (Learn Verilog HDL with Naresh Singh Dobal Series).</td></tr>
</tbody></table>
</span></div>
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<span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt;">
</span></div>
<div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><u><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt;">Design
Specification –</span></u><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"> Design specification is the state
at which we define the important parameters like – consider a system / design
of counter then specify start point, end point, length of counter, should have
synchronous reset, reset is at logic high, at reset output should be ‘0’ etc.</span></b></div>
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<b>
</b><br />
<div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Design specification include Market
Requirement Documents (MRD Sheet), High Level Design, Low / Micro Level Design
and RTL Coding Part.</span></b></div>
<b>
</b><br />
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<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">
</span></b></div>
<b>
</b><br />
<div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Design specification process starts
from the MRD Sheet (Market Requirement Documents), This outlines the
requirements of a new product. This section covers the market needs, the
customer value proposition, and product functionality. It is developed by the
marketing team and upper level management.</span></b></div>
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<b>
</b><br />
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<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">
</span></b></div>
<b>
</b><br />
<div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"><u>High Level Design (HLD) -</u><span style="mso-spacerun: yes;"> </span>At this state we defined all the major
blocks of any complex system and also defines how they communicate or connected
to each other like consider a microcontroller then the major block ay be RAM,
ROM, Micro-Processor, Timer, Ports, ADC, Counters, etc.</span></b></div>
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<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">
</span></b></div>
<b>
</b><br />
<div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"><u>Low Level Design (LLD) -</u><span style="mso-spacerun: yes;"> </span>At this state we describes that how all major
blocks of main system / design will be implement. It contains details of State
Machines, Counters, MUX, Decoders, Internal registers etc. This phase need a
lot of time to implement.</span></b></div>
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<b>
</b><br />
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<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">
</span></b></div>
<b>
</b><br />
<div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"><u>RTL Coding<span style="mso-spacerun: yes;"> </span>-</u><span style="mso-spacerun: yes;"><u> </u> </span>At
this stage we convert our micro design into HDL (VHDL / </span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Verilog</span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"> HDL) code using synthesizable
constructs of language. This part consist of coding.</span></b></div>
<b>
</b><br />
<div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">In real life RTL Code means that how
the small modules and components are connected to each other or how data flows
threw registers but in HDL language any code or collection of statements that
are synthesizable are called RTL code.</span></b></div>
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<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">
</span></b></div>
<b>
</b><br />
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<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">
</span></b></div>
<b>
</b><br />
<div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"><u>Design Simulation<span style="mso-spacerun: yes;"> </span>-</u><span style="mso-spacerun: yes;">
</span>Simulation is the process of verifying the functional specification of
system. We use simulators for simulation purpose. To test weather the RTL code
meets the functional specification or not, we must see all the RTL block are
functioning correctly with all the possibilities. For that purpose we use test
benches. This takes 60 – 70 %of time in design verification. </span></b><br />
<br />
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjVskjM6u1E3ZqG4MIUAUdxN0mWCwarUAZUI2bT0NCIVzUUaV49jf3XleUH8hoUadKvF5i4i0_Qxlyd_oRw-dP5DciXLTLHJqhN9FnOxo87092wNxdorJFJe9vN1bJQdUKFBeWx7Am_3a9I/s1600/img11-8-2013-3.28.56+PM.jpg" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="244" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjVskjM6u1E3ZqG4MIUAUdxN0mWCwarUAZUI2bT0NCIVzUUaV49jf3XleUH8hoUadKvF5i4i0_Qxlyd_oRw-dP5DciXLTLHJqhN9FnOxo87092wNxdorJFJe9vN1bJQdUKFBeWx7Am_3a9I/s320/img11-8-2013-3.28.56+PM.jpg" width="320" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Design Simulation : Learn Verilog HDL with Naresh Singh Dobal Series</td></tr>
</tbody></table>
</div>
<b>
</b><br />
<div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Simulation are mainly two types.</span></b></div>
<b>
</b><br />
<div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">First is Functional Simulation or
Behavior Simulation – Functional simulation is the verification of
functionality in the term of waveforms without considering timing
specification.</span></b></div>
<b>
</b><br />
<div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Timing Simulation or SDF Simulation
– Timing simulation also called Gate level simulation needs complete synthesis,
place and route and timing details. In Timing simulation we consider all the
timing and other parameters for real time simulation by considering delay of
all Gate level </span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">netlist</span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">.</span></b></div>
<div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
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<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">
</span></b></div>
<b>
</b><br />
<div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"><u>Synthesis -</u><span style="mso-spacerun: yes;"> </span>Synthesis is the process in which synthesis
tool like design compiler (Xilinx XST or </span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">vivado</span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"> etc), take RTL in </span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Verilog</span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"> or VHDL, and convert that code into the Register Level </span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Netlist</span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"> according to target technology.</span></b><br />
<br />
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiJ_nJxPEYgBtha5DU5BgndjuZkOOHgcOEkgHl49JTxv6GRDBNZ4gCzMEZ82ynqCX3ub_ZgwXrps4p_4La0T-oErJETWGttYtLE3E9t9xTqNpaWIjyV7RNhMX9GAD6jc9k8XlXs6BsXFQhf/s1600/img11-8-2013-3.30.00+PM.jpg" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="242" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiJ_nJxPEYgBtha5DU5BgndjuZkOOHgcOEkgHl49JTxv6GRDBNZ4gCzMEZ82ynqCX3ub_ZgwXrps4p_4La0T-oErJETWGttYtLE3E9t9xTqNpaWIjyV7RNhMX9GAD6jc9k8XlXs6BsXFQhf/s320/img11-8-2013-3.30.00+PM.jpg" width="320" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Design Synthesis : Learn Verilog HDL with Naresh Singh Dobal Series.</td></tr>
</tbody></table>
</div>
<b>
</b><br />
<div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Formal Verification – Check if the
RTL to gate mapping is correct.</span></b></div>
<b>
</b><br />
<div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Scan Insertion – Insert the scan
chain in case of ASIC.</span></b></div>
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<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">
</span></b></div>
<b>
</b><br />
<div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"><u>Place & Route -</u><span style="mso-spacerun: yes;"><u> </u> </span>The gate – level </span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">netlist</span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"> from the synthesis tool is taken
and imported into place & route tool in </span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">verilog</span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"> or </span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">vhdl</span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"> </span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">netlist</span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"> format, all the flip flops and
gates are placed and routed according to place and route (PNR) tool, P&R
tool generate GDS file used by foundry for ASIC Verification.</span></b></div>
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<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"><u>Configuration -</u> This is the Implementation stage where we configure our FPGA Devices according to our requirement or RTL Structures. Now the configured device ready for real life testing and application use. </span></b></div>
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<b><u><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Post </span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Sil</span></u><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"><u>. Validation </u>– Once the chip is back from fabrication, It
need to put in real environment for testing before sending it to market. Se we
need post silicon validation step.</span></b></div>
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<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">
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<div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">I would love to read your comments
and suggestions in comment bar below…</span></b></div>
<b>
</b><br />
<div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">My name is “Naresh Singh Dobal”, for
any query you can write us directly at<span style="mso-spacerun: yes;">
</span>nsdobal@gmail.com</span></b></div>
<b>
</b><br />
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Anonymoushttp://www.blogger.com/profile/03989667403249817442noreply@blogger.com1tag:blogger.com,1999:blog-5787558607075038825.post-2770867964254913842013-11-08T00:07:00.004-08:002013-11-08T00:07:51.607-08:00What a Designer can do using Verilog HDL -<div dir="ltr" style="text-align: left;" trbidi="on">
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<span style="font-size: large;"><b><u><span style="background-color: #f9cb9c;">What a Designer can do using Verilog HDL -</span></u></b></span><br />
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<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEj3FYg0VoLmKS9womtK0I88LsvgYayllLxQvl8hP-P5XKzBFIe8KFlXlPa0OmQJyX8q71dqMgR3vBFy5wDjI0ZN1MzZg1VyGPoKbid06BY1x16Jpmbr1Thf_p0O3PeEpis7UY6d-GlJmRm-/s1600/img11-8-2013-1.35.31+PM.jpg" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEj3FYg0VoLmKS9womtK0I88LsvgYayllLxQvl8hP-P5XKzBFIe8KFlXlPa0OmQJyX8q71dqMgR3vBFy5wDjI0ZN1MzZg1VyGPoKbid06BY1x16Jpmbr1Thf_p0O3PeEpis7UY6d-GlJmRm-/s1600/img11-8-2013-1.35.31+PM.jpg" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;"><span style="color: #222222; font-family: Arial, Verdana; font-size: 11px; line-height: 20px;">What a Designer can do using VerilogHDL : (Learn Verilog HDL with Naresh Singh Dobal series).</span></td></tr>
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<div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt;">Now
next thing is What you we do</span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"> with the Help of HDL’s-</span></b></div>
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</b><div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">So here I can say that you can
design a complete electronics part of any system with the help of HDL’s, You
can design any type of circuits like a complete robot system design, a home
automation system, security system, life style appliances, Industry automation
system, PLC’s etc, You can design a microprocessor or a microcontroller of your
own configuration according to your requirement, you can design a computer on
chip etc.</span></b></div>
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</b><div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Second most widely used application
of HDL’s are you can directly configure your design or system on Hardware with
the help of PLD’s, There are multiple type and class of PLD’s like PAL
(Programmable Array Logic), PLA (Programmable Logical Array). SPLD (Simple
Programmable Logical Devices), CPLD (Complex Programmable Logical Devices),</span></b></div>
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</b><div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">PROM (Programmable ROM), FPGA (Field
Programmable Gate Array), ASIC ( Application Specific Integrated Circuit).
Among these FPGA & ASIC are widely used for configuration. That means with
the help of FPGA devices we can directly configure our system on Hardware and
can test our design in real time environment.</span></b></div>
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<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">
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<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">
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</b><div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">I would love to read your comments
and suggestions in comment bar below…</span></b></div>
<b>
</b><div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">My name is “Naresh Singh Dobal”, for
any query you can write us directly at<span style="mso-spacerun: yes;">
</span>nsdobal@gmail.com</span></b></div>
<div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
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Anonymoushttp://www.blogger.com/profile/03989667403249817442noreply@blogger.com0tag:blogger.com,1999:blog-5787558607075038825.post-78378932028503478312013-11-08T00:04:00.002-08:002013-11-08T00:04:21.659-08:00What is the Need of HDL in Designing of Today's Complex Structures -<div dir="ltr" style="text-align: left;" trbidi="on">
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<b><u style="background-color: #f9cb9c;"><span style="font-size: medium;">What is the Need of HDL in Designing of Today's Complex Structures -</span></u></b><br />
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<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhGvHy_zpAQJenyZfYxGXTbhaPEiVaMMX-FsRUCh_ktarwd55KYs06HKNh0IAWP0CrVyxiBumPcHy1E21hY_z__zmLmrgt477BQGRJ-ZJ_wfFkpmMzZPvq-rg29B8QHZwb1vOo28Cd0s7aH/s1600/img11-8-2013-1.32.35+PM.jpg" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhGvHy_zpAQJenyZfYxGXTbhaPEiVaMMX-FsRUCh_ktarwd55KYs06HKNh0IAWP0CrVyxiBumPcHy1E21hY_z__zmLmrgt477BQGRJ-ZJ_wfFkpmMzZPvq-rg29B8QHZwb1vOo28Cd0s7aH/s1600/img11-8-2013-1.32.35+PM.jpg" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;"><span style="color: #222222; font-family: Arial, Verdana; font-size: 11px; line-height: 20px;">What is the need of HDL Languages : (Learn Verilog HDL with Naresh Singh Dobal series).</span> </td></tr>
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<b><span style="font-family: Arial; font-size: 12pt;">This
is the most Important Question ever, that</span><span style="font-family: Arial; font-size: 12pt; vertical-align: baseline;"> Why we need of HDL’s, and what we
loose without HDL’s?</span></b>
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<span style="vertical-align: baseline;"><span style="font-family: Arial; font-size: x-small;"><b> <span style="font-size: small;">For giving the answer of that
question more </span></b></span><span style="font-size: small;"><b><span style="font-family: Arial;">effectively</span><span style="font-family: Arial;"> I am going few decades back, As
we discussed previously in early circuit designing (manual designing) or In
late of 70’s the circuit designers designed their system with the help of truth
tables, Boolean mathematics, K-maps and other expression solving techniques.
But chip density and complexity was increasing continuously and then thousands of gates in a single chip
was common and for designing that system was not the easy task for engineers.
So Researchers planned some new techniques for designing and verification and
invented a totally different concept called HDL
Based Designing and Verification. And second thing early designer and
verification engineers worked on the Printed Circuit Boards or on Bread Boards
for test and verify their designs, but that was not the practical approach to
verify designs because that takes too much time and also the verification
engineers was not sure about the verification. There are multiple reasons
behind that like if engineer used 1000 gates in verification that first he have
to check the response of all the 1000 gates, because if any one of the gates
not works properly then we may get the wrong result. That means each gate must
be checked before using in logical verification which was not practically
possible.</span></b></span></span><b><span style="font-family: Arial; font-size: 12pt; vertical-align: baseline;"> </span><span style="font-family: Arial; font-size: 12pt; vertical-align: baseline;">That means testing of large
circuits was not possible because the large circuits contain lots of gates and
the response of each and every gate could not be checked.</span></b></div>
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<span style="font-family: Arial; font-size: 12pt; vertical-align: baseline;"><b>Second thing the time needed for
logical designing, In early days or in manual designing a large team was needed
for designing and more time was needed. After using of HDL’s designing time was
shorted because HDL’s are ready to work on sequential execution of statements
and the designers only have to write their requirements in the term of language
and then synthesis tools convert that High level language into Structural or
RTL level or Gate level Design. Hence using HDL’s Circuit Designing was very
easy through computer and then we can also develop these codes on hardware
using PLD’s. and save time and money.</b></span></div>
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<span style="font-family: Arial; font-size: 12pt; font-weight: bold;">Kindly
share your comments, ideas, questions or suggestions to make this series
interactive and more informative.</span></div>
<div style="direction: ltr; margin-bottom: 0pt; margin-top: 4.32pt; unicode-bidi: embed; vertical-align: baseline; word-break: normal;">
<span style="font-family: Arial; font-size: 12pt; font-weight: bold;"><br />
</span></div>
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<span style="font-family: Arial; font-size: 12pt; font-weight: bold;">Contact
US -</span></div>
<div style="direction: ltr; margin-bottom: 0pt; margin-top: 4.32pt; unicode-bidi: embed; vertical-align: baseline; word-break: normal;">
<span style="font-family: Arial; font-size: 12pt; font-weight: bold;">Naresh
Singh Dobal</span><span style="font-family: Arial; font-size: 12pt;"><br />
</span><span style="font-family: Arial; font-size: 12pt; font-weight: bold;">nsdobal@gmail.com</span></div>
<br /></div>
Anonymoushttp://www.blogger.com/profile/03989667403249817442noreply@blogger.com0tag:blogger.com,1999:blog-5787558607075038825.post-72336595614463982932013-11-08T00:01:00.001-08:002013-11-08T00:01:24.223-08:00Summary : A Brief History about Verilog HDL -<div dir="ltr" style="text-align: left;" trbidi="on">
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<span style="background-color: #fce5cd;"><span style="font-size: large;"><u><b>Summary : A Brief History about Verilog HDL -</b></u></span></span><br />
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<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiVrSINWfwAOFrh7_XJn2J9KapAfFdeUtb4gMzp-jDGJEyGuvdN04e2Kq_2ZaicTx0VFneiGgbFBuSchiqpL053nk8HhzaxUYQVT-BNYANTaTSWdslObiANqd-RywsKaXj2B-6BHpKHG0VR/s1600/img11-8-2013-1.29.27+PM.jpg" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiVrSINWfwAOFrh7_XJn2J9KapAfFdeUtb4gMzp-jDGJEyGuvdN04e2Kq_2ZaicTx0VFneiGgbFBuSchiqpL053nk8HhzaxUYQVT-BNYANTaTSWdslObiANqd-RywsKaXj2B-6BHpKHG0VR/s1600/img11-8-2013-1.29.27+PM.jpg" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Summary : History about Verilog HDL (Learn Verilog HDL with Naresh Singh Dobal Series).</td></tr>
</tbody></table>
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<div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<u><b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt;">Summary
about </span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt;">Verilog</span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt;"> HDL-</span></b></u><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"> </span></div>
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</span></div>
<div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Verilog</span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"> was developed in 1984-1985, Initially it was designed by
Automated Integrated Design System (AIDS) and later the language becomes the
property of Gateway Design Automation and later this was occupied by Cadence
and in 1990 Cadence opened this language for public and this became
standardized in 1995 by IEEE, and defined by standard IEEE-1364 and trademark
of Cadence.</span></b></div>
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<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">
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</b><div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Verilog</span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"> Development and promotions has been supported by OVI (Open </span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Verilog</span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"> International).</span></b></div>
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<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">
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</b><div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Records shows </span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Verilog</span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"> is much popular with ASIC designers
because. It is easy to learn, allows fast simulations and effective synthesis.</span></b></div>
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share your suggestions,</span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"> queries, comments or questions to
make this series more interactive and informative.</span></b></div>
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<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Regard-</span></b></div>
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</b><div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Naresh Singh Dobal</span></b></div>
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</b><div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">nsdobal@gmail.com</span></b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt;">
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Anonymoushttp://www.blogger.com/profile/03989667403249817442noreply@blogger.com0tag:blogger.com,1999:blog-5787558607075038825.post-87299256434475586222013-11-07T23:57:00.003-08:002013-11-08T00:14:48.986-08:00VLSI Major Classification (Front End and Back End Design) -<div dir="ltr" style="text-align: left;" trbidi="on">
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<span style="background-color: #fce5cd; font-family: Arial;"><b><u><span style="font-size: medium;">VLSI Major Classification (Front End and Back End Design) -</span></u></b></span><br />
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi0TqOglT5rDvh1T-eMeSZNTQ74kUJW2m3wdErCjfTROUsA_fNltQEFN1-ACnQ0hYGxNHMaFH45V7lz-iVkb56SNUzNTyNK0iWFZdorFRYhLVWbY6KXPIOj7b2orAuFfqRHFmbhDGjxtePx/s1600/img11-8-2013-1.25.39+PM.jpg" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi0TqOglT5rDvh1T-eMeSZNTQ74kUJW2m3wdErCjfTROUsA_fNltQEFN1-ACnQ0hYGxNHMaFH45V7lz-iVkb56SNUzNTyNK0iWFZdorFRYhLVWbY6KXPIOj7b2orAuFfqRHFmbhDGjxtePx/s1600/img11-8-2013-1.25.39+PM.jpg" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;"><span style="color: #222222; font-family: Arial, Verdana; font-size: 11px; line-height: 20px;">VLSI Major Classification (Learn Verilog HDL with Naresh Singh Dobal series).</span></td></tr>
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<b><span style="font-family: Arial; font-size: 12pt;">VLSI</span><span style="font-family: Arial; font-size: 12pt; vertical-align: baseline;">
Industry, - VLSI is mainly divided into two major domains, first one is called
VLSI Front End and second is VLSI Back End, As I told you previously that this
series is designed according to the practical approaches, labs and works, so I
am not going into deep, But you must differentiate these two domain to plan
your career in better way, The major different between them are –</span></b></div>
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<span style="font-family: Arial; font-size: 12pt; vertical-align: baseline;"><b>VLSI Front end considers all the
logical designing and verification part, In simple words we can say all the
work up to the Gate level or RTL Level designing and verification considered as VLSI Front End Designing and
Verification, We have multiple ways for logical designing of IC (Integrated
Circuits)’s in VLSI Front End, For Example in early days when we have very less
chip complexity, designers used Manual Logical Designing and they used concept
of number system, Basic Gates Concept, K-maps, Boolean Mathematics, expression
handling etc. </b></span></div>
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<span style="font-family: Arial; font-size: 12pt; vertical-align: baseline;"><b>As the time passed and according to
the Moore's law chip complexity has been
increased by multiple times and at that level logical designing was not
manageable using manual designing, So Schematics based Designing was
discovered, and we started work on computers and simulators, and We design our systems using Pick and
Place concept. In this concept we have some type of tool bars and all the basic
components and elements like basic gates, multiplexer, ALU, flip flops was
defined in the tool bars with there properties and user just pick that
component from the list and place it into the computer screen and then route
all the components with the help of wires. But at this level one thing is
common and this is designing methods, Using this concept we only optimized the
verification concept and this saved a lot of time and money. Because
verification needed more than twice of efforts (in term of time and money) as
compare to designing.</b></span></div>
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<span style="font-family: Arial; font-size: 12pt; vertical-align: baseline;"><b>But again these things failed as
the chip complexity increased, So researchers invented a totally different
concept of designing and verification. And that concept was HDL Based Designing
and Verification. And that concept was perfectly suited at that time for
complex chip design (or high density chips). These things reduces the Designing
Time and Cost and mainly the verification time. </b></span></div>
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<span style="font-family: Arial; font-size: 12pt; vertical-align: baseline;"><b>But now again HDL based designing
is exactly where, as the schematic based designing is as before 15 years,
because in now a days hundreds of pages of codes are not uncommon and this is
really very difficult to handle and manage designs and verification plans. So
now the question is What Will be the next ????????</b></span></div>
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<span style="font-family: Arial; font-size: 12pt; vertical-align: baseline;"><b>Second is VLSI Back End, that
consider all the designing and verification part after logical designing means
Gate level or RTL level designing, That may include Floor Planning, Place &
Route, and All the foundry work like fabrication, packaging etc. are also comes
in VLSI Back End.</b></span></div>
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<span style="font-family: Arial; font-size: 12pt; vertical-align: baseline;"><b><br /></b></span></div>
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<span style="font-family: Arial; font-size: 12pt; vertical-align: baseline;"><b>Kindly
share your comments, ideas, questions or suggestions to make this series
interactive and more informative.</b></span></div>
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<span style="font-family: Arial; font-size: 12pt; vertical-align: baseline;"><b><br /></b></span></div>
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<span style="font-family: Arial; font-size: 12pt; vertical-align: baseline;"><b>Contact
US -</b></span></div>
<div style="direction: ltr; margin: 4.32pt 0in 0pt; text-indent: 0in; unicode-bidi: embed; vertical-align: baseline; word-break: normal;">
<span style="font-family: Arial; font-size: 12pt; vertical-align: baseline;"><b>Naresh
Singh Dobal</b></span></div>
<div style="direction: ltr; margin: 4.32pt 0in 0pt; text-indent: 0in; unicode-bidi: embed; vertical-align: baseline; word-break: normal;">
<span style="font-family: Arial; font-size: 12pt; vertical-align: baseline;"><b>nsdobal@gmail.com</b></span></div>
</div>
</div>
Anonymoushttp://www.blogger.com/profile/03989667403249817442noreply@blogger.com0tag:blogger.com,1999:blog-5787558607075038825.post-77337025587146526502013-11-07T23:54:00.003-08:002013-11-08T00:13:25.334-08:00Series : Think Inside the box (Verilog HDL Design) with me "Naresh Singh Dobal" -<div dir="ltr" style="text-align: left;" trbidi="on">
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<span style="background-color: #fce5cd;"><span style="font-size: large;"><u><b><br /></b></u></span></span>
<span style="background-color: #fce5cd;"><span style="font-size: large;"><u><b>Series : Think Inside the box (Verilog HDL Design) with me "Naresh Singh Dobal" -</b></u></span></span><br />
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<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiJ0hXCa9VvFLQkjafAv2NdNR2w6QNKqhpQAj8kODW7UOiViB_ptKdDT0fWWiUD97BkxWmRdgSRDooBDgp_WFrUbmp6PjjAw_U3gRgYgZUJItuMbwhB9k_qwWlYkgpjaHlzm1jiognXsPvc/s1600/img11-8-2013-1.16.25+PM.jpg" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiJ0hXCa9VvFLQkjafAv2NdNR2w6QNKqhpQAj8kODW7UOiViB_ptKdDT0fWWiUD97BkxWmRdgSRDooBDgp_WFrUbmp6PjjAw_U3gRgYgZUJItuMbwhB9k_qwWlYkgpjaHlzm1jiognXsPvc/s1600/img11-8-2013-1.16.25+PM.jpg" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Think Inside The Box (Verilog HDL Design) "Learn verilog hdl with Naresh Singh Dobal Series".</td></tr>
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<b><span style="font-family: Arial; font-size: 12pt;">Hello</span><span style="font-family: Arial; font-size: 12pt; vertical-align: baseline;">
friends, After considering few of my last blogs I believe you </span><span style="font-family: Arial; font-size: 12pt; vertical-align: baseline;">got
</span><span style="font-family: Arial; font-size: 12pt; vertical-align: baseline;">the basic idea about our EDA &
Semiconductor Industry, and now you know that how the computer chips are
manufactured and how they are designed, so now you are aware </span><span style="font-family: Arial; font-size: 12pt; vertical-align: baseline;">about
the process that </span><span style="font-family: Arial; font-size: 12pt; vertical-align: baseline;">how this EDA industry is important for
VLSI Industry. Today I am going to tell you that how a designer / engineer
works with this EDA industry. I am going
to start this with the basics of HDL & most widely used HDL in digital electronics design </span><span style="font-family: Arial; font-size: 12pt; vertical-align: baseline;">i.e</span><span style="font-family: Arial; font-size: 12pt; vertical-align: baseline;">
Verilog HDL.</span></b></div>
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<span style="font-family: Arial; font-size: 12pt; vertical-align: baseline;"><b><br /></b></span></div>
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<span style="font-family: Arial; font-size: 12pt; vertical-align: baseline;"><b>So lets start with this educational series named, “Think Inside The Box” with me “Naresh Singh Dobal”.</b></span></div>
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<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEijEf1Tnwfup1GdSwencp57YJhM1IMqAB4MQ3E6GKlgZ9oKEeG8RzWizPflLIjspdWYzpZsEnBgBljewkMoYEi-p1MF-4uqb-fYtJNSbbnZMQfDJTNSO0yS7CZGcuDe88-2whQWSNnpIt8r/s1600/img11-8-2013-1.22.47+PM.jpg" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEijEf1Tnwfup1GdSwencp57YJhM1IMqAB4MQ3E6GKlgZ9oKEeG8RzWizPflLIjspdWYzpZsEnBgBljewkMoYEi-p1MF-4uqb-fYtJNSbbnZMQfDJTNSO0yS7CZGcuDe88-2whQWSNnpIt8r/s1600/img11-8-2013-1.22.47+PM.jpg" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">VHDL - A small Description (Learn Verilog HDL with Naresh Singh Dobal Series). </td></tr>
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<span style="font-family: Arial; font-size: 12pt; vertical-align: baseline;"><b> </b></span><b><span style="font-family: Arial; font-size: 12pt; vertical-align: baseline;">
</span></b></div>
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<div style="direction: ltr; language: en-US; margin-bottom: 0pt; margin-top: 4.32pt; mso-line-break-override: restrictions; punctuation-wrap: simple; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<span style="background-color: #fce5cd;"><u><b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Basics to </span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Verilog</span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"> HDL -</span></b></u></span></div>
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<b><span style="font-size: small;"><span style="color: black; font-family: Arial; vertical-align: baseline;">Verilog</span><span style="color: black; font-family: Arial; vertical-align: baseline;"> is very much popular with ASIC Designer because –</span></span></b></div>
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</span></b><div style="direction: ltr; margin-bottom: 0pt; margin-top: 4.32pt; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="font-size: small;"><span><span style="font-family: Arial;">•</span></span><span style="color: black; font-family: Arial; vertical-align: baseline;">Verilog</span><span style="color: black; font-family: Arial; vertical-align: baseline;"> is easy to learn and work.</span></span></b></div>
<b><span style="font-size: small;">
</span></b><div style="direction: ltr; margin-bottom: 0pt; margin-top: 4.32pt; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="font-size: small;"><span><span style="font-family: Arial;">•</span></span><span style="color: black; font-family: Arial; vertical-align: baseline;">Verilog</span><span style="color: black; font-family: Arial; vertical-align: baseline;"> allows fast simulation.</span></span></b></div>
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<b><span style="font-size: small;"><span><span style="font-family: Arial;">•</span></span><span style="color: black; font-family: Arial; vertical-align: baseline;">And more effective synthesis.</span></span></b></div>
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<b><span style="font-size: small;"><span style="color: black; font-family: Arial; vertical-align: baseline;"> </span></span></b></div>
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<b><span style="font-size: small;"><span style="color: black; font-family: Arial; vertical-align: baseline;">
</span></span></b></div>
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</span></b><div style="direction: ltr; margin-bottom: 0pt; margin-top: 4.32pt; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="font-size: small;"><span style="color: black; font-family: Arial; vertical-align: baseline;">Verilog</span><span style="color: black; font-family: Arial; vertical-align: baseline;"> is a type of HDL Language where HDL is (Hardware
Description Language). Also </span><span style="color: black; font-family: Arial; vertical-align: baseline;">Verilog</span><span style="color: black; font-family: Arial; vertical-align: baseline;"> is promoted by OVI (Open Verification International).</span></span></b></div>
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<b><span style="font-size: small;"><span style="color: black; font-family: Arial; vertical-align: baseline;">
</span></span></b></div>
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<b><span style="font-size: small;"><span style="color: black; font-family: Arial; vertical-align: baseline;">Here Hardware Description
represents<span> </span>the whole description of
electronics circuits in the term of flow of data, schematic design or
interconnection of components and in the terms of functions or truth table. </span></span></b></div>
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</span></b><div style="direction: ltr; margin-bottom: 0pt; margin-top: 4.32pt; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="font-size: small;"><span style="color: black; font-family: Arial; vertical-align: baseline;">
</span></span></b></div>
<b><span style="font-size: small;">
</span></b><div style="direction: ltr; margin-bottom: 0pt; margin-top: 4.32pt; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="font-size: small;"><span style="color: black; font-family: Arial;">Integrated
Circuits<span> </span>represents</span><span style="color: black; font-family: Arial; vertical-align: baseline;"> Digital IC.</span></span></b></div>
<b><span style="font-size: small;">
</span></b><div style="direction: ltr; margin-bottom: 0pt; margin-top: 4.32pt; text-align: left; unicode-bidi: embed; vertical-align: baseline;">
<b><span style="font-size: small;"><span style="color: black; font-family: Arial;">
</span></span></b></div>
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<b><span style="font-size: small;"><span style="color: black; font-family: Arial;">Language<span> </span>means a set of standards</span><span style="color: black; font-family: Arial; vertical-align: baseline;">, codes and commands.</span></span></b></div>
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<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt;">Kindly
share your suggestions,</span><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;"> queries, comments or questions to
make this series more interactive and informative.</span></b></div>
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<b><span style="color: black; font-family: Arial; font-size: 12.0pt; language: en-US; mso-ascii-font-family: Arial; mso-bidi-font-family: +mn-cs; mso-color-index: 1; mso-fareast-font-family: +mn-ea; mso-font-kerning: 12.0pt; mso-text-raise: 0%; vertical-align: baseline;">Regard-</span></b></div>
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Anonymoushttp://www.blogger.com/profile/03989667403249817442noreply@blogger.com0tag:blogger.com,1999:blog-5787558607075038825.post-57677716160968224012013-07-30T04:09:00.000-07:002013-07-30T04:09:07.872-07:00The Three Basic Element inside a Computer Chip -<div dir="ltr" style="text-align: left;" trbidi="on">
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<b><u style="background-color: #fce5cd;"><span style="font-size: large;">Three Basic Element inside a Compute Chip -</span></u></b><br />
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<tr><td class="tr-caption" style="text-align: center;">Three Basic Elements inside IC (Learn Verilog with Naresh Singh Dobal Series).</td></tr>
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<b><span style="font-family: 'Courier New', Courier, monospace;"><span style="color: black; font-size: 12pt; vertical-align: baseline;"> There are three basic elements in a computer chip, First one is called a transistor and this is the switch just like a light switch, that turn on or off, and flows and block the electricity, this is the three terminal device. </span></span></b></div>
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<b><span style="font-family: 'Courier New', Courier, monospace;"><span style="color: black; font-size: 12pt; vertical-align: baseline;"> Next one is resistor, and resistor slows down the electricity, when electricity passes threw the resistor then it resist the flow of electricity, it’s symbol is like a zigzag line, and this is a two terminal device, and this is very important in electronics, Resistors comes in different values and different sizes. If you see them in real then you can see some band of colors these band actually tells the value of resistance, don’t worry about that I will tell you that how you can identify the value of resistors using color bands.</span></span></b></div>
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<b><span style="font-family: 'Courier New', Courier, monospace;"><span style="color: black; font-size: 12pt; vertical-align: baseline;"> The third most important part of an integrated circuit or computer chip is capacitor, and a capacitor stores the electricity, These capacitors makes up of different materials and different sizes, this is basically a two terminal component.</span></span></b></div>
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<b><span style="font-family: 'Courier New', Courier, monospace;"><span style="color: black; font-size: 12pt; vertical-align: baseline;">So now if you connect these all components a resistor, transistor and capacitors with the help of wires then you have a some type of electronic circuit. </span></span></b></div>
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Anonymoushttp://www.blogger.com/profile/03989667403249817442noreply@blogger.com0tag:blogger.com,1999:blog-5787558607075038825.post-82884669772992746482013-07-30T04:06:00.001-07:002013-07-30T04:06:54.272-07:00Let's start with making a Semiconductor Chip -<div dir="ltr" style="text-align: left;" trbidi="on">
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<b><u style="background-color: #fce5cd;"><span style="font-size: large;">Lets start with making a Semiconductor Chip -</span></u></b><br />
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<tr><td class="tr-caption" style="text-align: center;">Let's start with making a semiconductor chip (Learn Verilog with Naresh Singh Dobal series).</td></tr>
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<b><span style="font-family: 'Courier New', Courier, monospace;"><span style="color: black; font-size: 12pt;"> So now let’s talk about that</span><span style="color: black; font-size: 12pt; vertical-align: baseline;"> how do you make these amazing computer chips. Before that we should understand what are Integrated circuits, just think like that, a chip is a switch like a light switch, when you turn on the switch then the electricity goes threw it, and light will turn on, and when switch is off, then it’s blocks the current and light will off. So in the case of semiconductor it’s partially conduct the electricity threw it. So when it is ON electricity goes threw it and light will on, and when it is off then its blocks the current and light will off. So now you know every thing about the chip, that they are simply the switch, Cool </span><span style="color: black; font-size: 12pt; vertical-align: baseline;">na</span><span style="color: black; font-size: 12pt; vertical-align: baseline;">… so now you may surprise that </span><span style="color: black; font-size: 12pt; vertical-align: baseline;">ohhh</span><span style="color: black; font-size: 12pt; vertical-align: baseline;"> the computer chips are only just like switch! But this is little bit complicated than that, The important thing about these switch are they are made up of sand, and in our semiconductor industry it’s means to silicon. Silicon is the most abundant element on earth. This is very good material to integrate these switches. I recently learn that most of the sand comes from Australia. Because there sand is more pure. </span></span></b></div>
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<b><span style="font-family: 'Courier New', Courier, monospace;"><span style="color: black; font-size: 12pt; vertical-align: baseline;"> So now lets talking about the switches, so there are two switches, and you can see at the left when switch is off, then there is no flow of electrons and no flow of current, and in the right image when switch is on, the electrons flows to the other terminal and current flows, so turn these switches on and off like turn it on, turn it off, turn it on and so on, the electricity flows and blocks, according to switch through out the computer chips. Very simple it is.</span></span></b></div>
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Anonymoushttp://www.blogger.com/profile/03989667403249817442noreply@blogger.com0tag:blogger.com,1999:blog-5787558607075038825.post-73611263451761697932013-07-30T04:04:00.002-07:002013-07-30T04:04:33.536-07:00Let's Know about our Semiconductor Industry -<div dir="ltr" style="text-align: left;" trbidi="on">
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<b><span style="font-family: 'Courier New', Courier, monospace;"> So friends, why we are here, I mean to this semiconductor industry. Obviously to make a lot of money, so lets talk about the industry in general, that how important we are, what we do, and how we can make money from this industry, First I would like to tell you some fact about this industry that how big actually this semiconductor industry is, means how much cost of computer chips resell each year, this is approximately 300 billion dollars, this records is according to the year 2010 but today is 2013, so that numbers must be higher, that is our gole, if we talking about the EDA industry then that is about 5.3 billion dollars, The interesting thing is that none of the computer chip and electronic chip will be exist without this EDA industry.</span></b></div>
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<b><span style="font-family: 'Courier New', Courier, monospace;"> Now the market drivers, that means to the selling of electronic chip to consumer, The most important thing about the market driver is time to market, that means you have to move the products to the market on time, this is because we generally knows this term that there are some occasions when the demands is high for example many of us plans to purchase a computer system or any other electronic gadgets on Diwali or other festivals, so at that peak time if company is not delivers the products, that reduces the profit, now another critical aspect which effect the vlsi industry is global competition, the chip industry or semiconductor industry was mainly based on US market, few years back Japanese said that they produce the electronic chip cheaper, faster and better quality, and they really affects the US semiconductor market, The US developer says ohhh we don't want to loose the semiconductor market, and takes some major steps. But interesting thing is that, now the semiconductor or chip industry is approximately all over the world. primarily in twain. This was quite interesting. And other aspects are the technology which is use to make chips smaller, faster denser, and lower cost and better quality. Because if you remember the early cell phones they are bigger at 10000Rs, but today you will get these cell phones in 500Rs only, so the cost is lower and lower, and size of systems is also reduces, and it's now smaller, smaller and smaller, so I must say that this technology is very interesting, dynamic, and challenging.</span></b></div>
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Anonymoushttp://www.blogger.com/profile/03989667403249817442noreply@blogger.com0tag:blogger.com,1999:blog-5787558607075038825.post-52753639197218668432013-07-30T04:02:00.004-07:002013-07-30T04:02:52.360-07:00Computer Chips are Every-Where (Application of Electronics Chips). <div dir="ltr" style="text-align: left;" trbidi="on">
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<b><span style="font-family: 'Courier New', Courier, monospace;"> Yes, This is right Computer chips are absolutely every where and in every field, even that places you dont't imagine, so they are in your computers and cellular phones, in your tablets, they are in your gaming systems like xbox, play stations, they are in i-pods, DVD Players, TV's, watches, They are in automobile like cars, bikes, etc pacemakers, satellites, electronic greeting cards like when you open that some type of sound play from it, So you can say that electronics chips are every where - In communication, medical, Industrial automation, PLC devices, controlling instruments, Electronic gadgets, daily use appliances, in traffic lights etc.</span></b></div>
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Anonymoushttp://www.blogger.com/profile/03989667403249817442noreply@blogger.com0tag:blogger.com,1999:blog-5787558607075038825.post-402435505344405822013-07-30T04:00:00.002-07:002013-07-30T04:00:33.650-07:00Very Important ACRONYMS & TERMS of Semiconductor Industry :<div dir="ltr" style="text-align: left;" trbidi="on">
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<b><u style="background-color: #fce5cd;"><span style="font-size: large;">Important ACRONYMS - </span></u></b><br />
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<tr><td class="tr-caption" style="text-align: center;">Important Acronyms & Terms of Semiconductor Industry (Learn Verilog with Naresh Singh Dobal).</td></tr>
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<span style="color: #222222; font-family: 'Courier New', Courier, monospace; font-size: 14px; line-height: 20px;"><b> So Friends my first question to you is, that what we are, in this electronic semiconductor industry, We are EDA, i.e Electronic Design Automation, As the name indicates that we automating the design of electronics, That means we use computers to design all these complicated chips that may be used in Ipods, Laptops, Display systems, Sound systems, cell-phones, Tablets, Industry automation system, security system, medical etc. </b></span><br style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;" /><span style="color: #222222; font-family: 'Courier New', Courier, monospace; font-size: 14px; line-height: 20px;"><b><br /></b></span><span style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"></span><span style="color: #222222; font-family: 'Courier New', Courier, monospace; font-size: 14px; line-height: 20px;"><b> The next important thing is CAD that is Computer Aided Design, in the past few deades we are using CAD Tools in every field like mechanical design, civil design, automobile design, IC design, system design etc.</b></span><br style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;" /><span style="color: #222222; font-family: 'Courier New', Courier, monospace; font-size: 14px; line-height: 20px;"><b><br /></b></span><span style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"></span><span style="color: #222222; font-family: 'Courier New', Courier, monospace; font-size: 14px; line-height: 20px;"><b> This is the very important thing in EDA industry that is HDL called Hardware Description Language. This is actually a computer Language, This is very important in VLSI Industry, using HDL we tell the computer to help in design of any integrated circuit, HDL's are working on the same manner that other programming language works that you give some commands to the computer, like computer do this, computer do that .. in this manner. There are many HDL's in market, Here I am telling you about the most popular HDL i.e VHDL.</b></span><br style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;" /><span style="color: #222222; font-family: 'Courier New', Courier, monospace; font-size: 14px; line-height: 20px;"><b><br /></b></span><span style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"></span><span style="color: #222222; font-family: 'Courier New', Courier, monospace; font-size: 14px; line-height: 20px;"><b> VHDL, stands for Very High Speed Integrated Circuit Hardware Description Language. Another popular language is Verilog & System Verilog. So as all other competitive languages there is a language war, that some says VHDL is better, some says no Verilog is good, and some says System Verilog is good. But this is not in that manner, all the language do the same thing but in different manner, It's just like same, some says English is good, some says hindi is good. So people can choose that which they want to use. This may be choose by designer, or by a company or Country wise as well.</b></span><br style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;" /><span style="color: #222222; font-family: 'Courier New', Courier, monospace; font-size: 14px; line-height: 20px;"><b><br /></b></span><span style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"></span><span style="color: #222222; font-family: 'Courier New', Courier, monospace; font-size: 14px; line-height: 20px;"><b> The next important term is RTL, RTL stands for Register Transfer Level, This is very common term used in EDA industry, This is basically a collection of subsets or collection or commands or the blocks of electronic components having some type of combination or sequential circuit or the basic logical gates.</b></span><br style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;" /><span style="color: #222222; font-family: 'Courier New', Courier, monospace; font-size: 14px; line-height: 20px;"><b><br /></b></span><span style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"></span><span style="color: #222222; font-family: 'Courier New', Courier, monospace; font-size: 14px; line-height: 20px;"><b> PLD's are Programmable Logical Devices, as name suggests, that the devices which can Program a Logic inside it are named as PLD's. There are many type of PLD's in market like PLA (Programmable Logic Array), PAL (Programmable Array Logic), PROM (Programmable ROM), SPLD (Simple PLD), CPLD (Complex PLD), FPGA (Field Programmable Gate Array), ASIC (Application Specific Integrated Circuit).</b></span><br style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;" /><span style="color: #222222; font-family: 'Courier New', Courier, monospace; font-size: 14px; line-height: 20px;"><b><br /></b></span><span style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"></span><span style="color: #222222; font-family: 'Courier New', Courier, monospace; font-size: 14px; line-height: 20px;"><b> ASIC stands for Application Specific Integrated Circuit. First we take a example of general purpose chips like a intel processor, I put that chip in a microwave oven and I say cook my food, and then i places that chip into a traffic light and I say "change the signals according to traffic density", then I put that chip into a security system and say when some one enter in my room then play some sound, Or i place it into a mobile and say ring when someone is calling me, So this a a example of general purpose chips, but if i want a chip that only performs a one very tiny tiny specific function that no other chip can do.So that chip is very much specific to my own application, so lets say I want to make a chip which only tell me when some one walks in my home, that can be specific function, so ASIC are the specific type of chips.</b></span><br style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;" /><span style="color: #222222; font-family: 'Courier New', Courier, monospace; font-size: 14px; line-height: 20px;"><b><br /></b></span><span style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"></span><span style="color: #222222; font-family: 'Courier New', Courier, monospace; font-size: 14px; line-height: 20px;"><b> FPGA : FPGA stands for Field Programmable Gate Array. This is a special type of chip, which can be use for general application, and the more things about FPGA's We will discuss later. When we work on that chips.</b></span><br style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;" /><span style="color: #222222; font-family: 'Courier New', Courier, monospace; font-size: 14px; line-height: 20px;"><b><br /></b></span><span style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"></span><span style="color: #222222; font-family: 'Courier New', Courier, monospace; font-size: 14px; line-height: 20px;"><b> Platform : Platform is basically a foundation where some thing can be stand, but if we talk about VLSI industry then platform means the collection of EDA tools.</b></span><br style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;" /><span style="color: #222222; font-family: 'Courier New', Courier, monospace; font-size: 14px; line-height: 20px;"><b><br /></b></span><span style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"></span><span style="color: #222222; font-family: 'Courier New', Courier, monospace; font-size: 14px; line-height: 20px;"><b> IP : This is a very important term in EDA industry, that may confuse to you with the IP i.e. Internet Protocol, but we nothing to do from that IP in our industry. In our industry IP stands for intellectual property, and there is mainly two expect of intellectual property. So what is Intellectual Property, these are our ideas or inventions or creations which are generated in our head and the reason of intellectual property is so important because if some one steal your ideas and do's that same things, and often gets money it's not related to there business but it's hurts, and This is really a bad thing. So our industry plans of IP. Using these IP we protect the intellectual properties with legal agreements, so intellectual properties is very very important, the second things about the intellectual property is also mean design, chip design and if I come with this brilliant idea of design but I want to protect that and I also want to reuse that so I can build bigger things at top level, so IP's are the building blocks in a comlex chip designs. And we can use that in the top level designs. Fact is There are thousands of employees works in a industry, but the major thing is ideas, mind, creations, logical thinking, designing abilities.</b></span><br style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;" /><span style="color: #222222; font-family: 'Courier New', Courier, monospace; font-size: 14px; line-height: 20px;"><b><br /></b></span><span style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"></span><span style="color: #222222; font-family: 'Courier New', Courier, monospace; font-size: 14px; line-height: 20px;"><b> Semiconductor : Semiconductor, I am explaining this term in very simple way, semi means partial, conductor means conducting of electricity so what is semiconductor means that some other time this conduct the current threw it or some other times this blocks the electricity.</b></span><br style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;" /><br style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;" /><span style="color: #222222; font-family: 'Courier New', Courier, monospace; font-size: 14px; line-height: 20px;"><b> IC : IC are integrated circuits or integrated chips.</b></span><br style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;" /><span style="color: #222222; font-family: 'Courier New', Courier, monospace; font-size: 14px; line-height: 20px;"><b> </b></span><br style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;" /><span style="color: #222222; font-family: 'Courier New', Courier, monospace; font-size: 14px; line-height: 20px;"><b><br /></b></span><span style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"></span><span style="color: #222222; font-family: 'Courier New', Courier, monospace; font-size: 14px; line-height: 20px;"><b><br /></b></span><span style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"></span><span style="color: #222222; font-family: 'Courier New', Courier, monospace; font-size: 14px; line-height: 20px;"><b><br /></b></span><span style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"></span><br style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;" /><span style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"> </span><b style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"> <span style="background-color: #e06666;"> Previous Page </span> <span style="background-color: #e06666;"> Next Page </span></b></div>
Anonymoushttp://www.blogger.com/profile/03989667403249817442noreply@blogger.com0tag:blogger.com,1999:blog-5787558607075038825.post-61851985898972305582013-07-30T03:58:00.001-07:002013-07-30T03:58:03.359-07:00Electronics - Trends Setting Points <div dir="ltr" style="text-align: left;" trbidi="on">
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<tr><td class="tr-caption" style="text-align: center;">Electronics : Trend Setting Points (Learn Verilog with Naresh Singh Dobal Series)</td></tr>
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<b style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"> <span style="font-family: Arial, Helvetica, sans-serif;">First I would like to tell you few interesting things about the trends setting point of this semiconductor industry and electronics. According to a record that is found that the word "electronics" has first comes in 1894, Mainly in 1946 or before our early electronics computers use glass valves they called vacuumed tubes. What very interesting that the first electronics computer called INAC that have 18000 valves, that have a weight of 30 tons and takes the power required for the 10 homes. So amazing today's now we dont' take a computer having the weight of 30 tons, now you have the small computers in 1-2 kg only or may be less. Basically the early glass valves glows and produced heat to perform operations. So we have to use very effective cooling environment and ventilation system and the important thing is that when the system fails the debugging of these valves were very difficult.</span></b><br style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;" /><br style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;" /><span style="color: #222222; font-family: Arial, Helvetica, sans-serif; font-size: 14px; line-height: 20px;"><b> In 1947 a first transistor was developed in bell labs, don't worry I will show you a transistor after some time, Early Transistors are near about 40 to 45 dollars, and now the transistors are only 15 cents or less.</b></span><br style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;" /><span style="color: #222222; font-family: Arial, Helvetica, sans-serif; font-size: 14px; line-height: 20px;"><b><br /> In 1954 a fully Transistorised computer was developed and it was invented by IBM, and this take 2000 separate transistors.</b></span><br style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;" /><span style="color: #222222; font-family: Arial, Helvetica, sans-serif; font-size: 14px; line-height: 20px;"><b><br /></b></span><span style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"></span><span style="color: #222222; font-family: Arial, Helvetica, sans-serif; font-size: 14px; line-height: 20px;"><b> In 1958 the first integrated circuit normally called IC was invented at Texas Instruments.</b></span><br style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;" /><span style="color: #222222; font-family: Arial, Helvetica, sans-serif; font-size: 14px; line-height: 20px;"><b><br /></b></span><span style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"></span><span style="color: #222222; font-family: Arial, Helvetica, sans-serif; font-size: 14px; line-height: 20px;"><b> In 1971 the first microprocessor was invented by INTEL, this first microprocessor having 2300 integrated transistors, INTEL - you know about intel that is in intel inside logo, most of the computers and laptops in today life are working on INTEL processors.</b></span><br style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;" /><span style="color: #222222; font-family: Arial, Helvetica, sans-serif; font-size: 14px; line-height: 20px;"><b><br /></b></span><span style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"></span><span style="color: #222222; font-family: Arial, Helvetica, sans-serif; font-size: 14px; line-height: 20px;"><b> In 1975, this is the most important concept which was developed, and the concept was that the chip complexity i.e How much components or transistors implemented on a single chip, it was predicted that the chip complexity will be double in every 1 and half years, This concept is called Moore's Law in our industry, But His original prediction was in 1965, and He said that the number of transistors will be twice in each and every year. But in 1975 after 10 years of that prediction what they found that the chip complexity will be double in every 2 years. So our industry decided according to moore's law and result of last decade that the chip complexity will be twice in every one and half year (18 months), and till this day that is 2013 the moore's law continuously running in the industry.</b></span><br style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;" /><span style="color: #222222; font-family: Arial, Helvetica, sans-serif; font-size: 14px; line-height: 20px;"><b><br /></b></span><span style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"></span><span style="color: #222222; font-family: Arial, Helvetica, sans-serif; font-size: 14px; line-height: 20px;"><b> In the last point of that history in year 2011 the INTEL again introduced 10 core xion weasteren processor, This particular microprocessor has 2 billion 600 million transistors in a size of your finger point.</b></span><br style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;" /><br style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;" /><br style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;" /><br style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;" /><br style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;" /><br style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;" /><br style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;" /><span style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"> </span><b style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"> <span style="background-color: #e06666;"> Previous Page </span> <span style="background-color: #e06666;"> Next Page </span></b><br />
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Anonymoushttp://www.blogger.com/profile/03989667403249817442noreply@blogger.com0tag:blogger.com,1999:blog-5787558607075038825.post-6166741715331285792013-07-30T03:55:00.001-07:002013-07-30T03:55:31.444-07:00World of Integrated Chips AND Electronic Design -<div dir="ltr" style="text-align: left;" trbidi="on">
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<tr><td class="tr-caption" style="text-align: center;">World of Integrated Chips and Electronic Design with Naresh Singh Dobal.<br /><br /><br /><br /></td></tr>
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<b style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"> Welcome you ALL in the ERA of this Interactive session named "World of Integrated Chips and Electronic Design, I am "Naresh Singh Dobal", and I am going to give you some amazing information's about our Semiconductor Industry.</b><br style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;" /><b style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"><br /></b><span style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"></span><b style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"> This small series will give you an idea about the VLSI chips, like how the computer chips are manufacture and how they are designed, This small Tutorial will develop a basic understanding of Semiconductor Industry, Don't Worry about this semiconductor term, I will explain that in my next session, and more about the EDA, EDA is Electronic Design Automation.</b><br style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;" /><b style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"><br /> I will tell you that how EDA are important to our semiconductor industry, because we actually in EDA a small industry, but we belongs to this great thing called Semiconductor Industry.</b><br style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;" /><b style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;">Also we will follow the very simplified steps to process the manufacturing of computer chips and their designing.</b><span style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"> </span><br style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;" /><b style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"><br /></b><span style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"></span><b style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"><br /></b><span style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"></span><b style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;">I really would love for everybody to ask questions to make this tutorial, a interactive series...</b><br style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;" /><br style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;" /><br style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;" /><br style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;" /><br style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;" /><span style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"> </span><b style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"><span style="background-color: #e06666;"> Next Page </span></b><span style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"> </span></div>
Anonymoushttp://www.blogger.com/profile/03989667403249817442noreply@blogger.com0tag:blogger.com,1999:blog-5787558607075038825.post-76709912725530948742013-07-30T03:44:00.001-07:002013-07-30T03:44:30.216-07:00Design of 8 to 3 Parity Encoder using if -else statements (Verilog CODE)<div dir="ltr" style="text-align: left;" trbidi="on">
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<b><u style="background-color: #fce5cd;"><span style="font-size: large;">Design of 8 to 3 Parity Encoder using if - else statements -</span></u></b><br />
<b><u style="background-color: #fce5cd;"><span style="font-size: large;"><br /></span></u></b>
<b><u style="background-color: #fce5cd;"><span style="font-size: large;"><br /></span></u></b>
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgJWDeEWt6y7XpfdriwlIjTW3FYI3_Ln_IsecuO99LaHWolOP-Z61Ug3xyuBeZp5ayUdj2Lu7gFAdRCK6HJq0JcnukhNI-Da1MEtURtxsDibslgzTzNFgZrv8OPz9R5kjYYTioit9G-U38R/s1600/img7-29-2013-3.23.34+PM.jpg" style="margin-left: auto; margin-right: auto;" /></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Output Waveform 1 : 8 to 3 Parity Encoder</td></tr>
</tbody></table>
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<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjJt6UgXyRDymtkfbI0cHEdfwcGeO3GUM1JKKmwVl8OCyPNkBsZMID6hbxpRLH2SZsmP-LD4lzpcZ_2jN0x013ObXuvYQTZ4r64zR-M-WSZDfz-JvrbHRF0-MzLo9ZTWupfxXGL-X8njcP2/s1600/img7-29-2013-3.21.11+PM.jpg" style="margin-left: auto; margin-right: auto;" /></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Output Waveform : 8 to 3 Parity Encoder</td></tr>
</tbody></table>
<b><u style="background-color: #fce5cd;"><span style="font-size: large;"><br /></span></u></b>
<b><u style="background-color: #fce5cd;"><span style="font-size: large;">Verilog CODE -</span></u></b><br />
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//-----------------------------------------------------------------------------<br />
//<br />
// Title : parity_encoder<br />
// Design : verilog upload 4<br />
// Author : Naresh Singh Dobal<br />
// Company : nsdobal@gmail.com<br />
// Verilog Programs & Exercise with Naresh Singh Dobal<br />
//<br />
//-----------------------------------------------------------------------------<br />
//<br />
// File : Parity Encoder using if else statement.v<br />
<br />
<br />
module parity_encoder ( din ,dout );<br />
<br />
output [2:0] dout ;<br />
reg [2:0] dout ;<br />
<br />
input [7:0] din ;<br />
wire [7:0] din ;<br />
<br />
<br />
always @ (din) begin<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>if (din[7])<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>dout = 0;<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>else if (din[6])<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>dout = 1;<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>else if (din[5])<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>dout = 2;<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>else if (din[4])<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>dout = 3;<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>else if (din[3])<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>dout = 4;<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>else if (din[2])<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>dout = 5;<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>else if (din[1])<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>dout = 6;<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>else if (din[0])<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>dout = 7;<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>else<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>dout = 3'bZZZ;<br />
end<br />
<br />
endmodule<br />
<div>
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</div>
Anonymoushttp://www.blogger.com/profile/03989667403249817442noreply@blogger.com2tag:blogger.com,1999:blog-5787558607075038825.post-1769297795899561682013-07-30T03:40:00.005-07:002013-07-30T03:40:53.036-07:00Design of 8 : 3 Parity Encoder using conditional operator<div dir="ltr" style="text-align: left;" trbidi="on">
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<b><u style="background-color: #fce5cd;"><span style="font-size: large;">Design of 8 : 3 Parity Encoder using Conditional Operator -</span></u></b><br />
<b><u style="background-color: #fce5cd;"><span style="font-size: large;"><br /></span></u></b>
<b><u style="background-color: #fce5cd;"><span style="font-size: large;"><br /></span></u></b>
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgJWDeEWt6y7XpfdriwlIjTW3FYI3_Ln_IsecuO99LaHWolOP-Z61Ug3xyuBeZp5ayUdj2Lu7gFAdRCK6HJq0JcnukhNI-Da1MEtURtxsDibslgzTzNFgZrv8OPz9R5kjYYTioit9G-U38R/s1600/img7-29-2013-3.23.34+PM.jpg" style="margin-left: auto; margin-right: auto;" /></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Output Waveform 1 : 8 to 3 Parity Encoder</td></tr>
</tbody></table>
<b><u style="background-color: #fce5cd;"><span style="font-size: large;"><br /></span></u></b>
<b><u style="background-color: #fce5cd;"><span style="font-size: large;"><br /></span></u></b>
<b><u style="background-color: #fce5cd;"><span style="font-size: large;"><br /></span></u></b>
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjJt6UgXyRDymtkfbI0cHEdfwcGeO3GUM1JKKmwVl8OCyPNkBsZMID6hbxpRLH2SZsmP-LD4lzpcZ_2jN0x013ObXuvYQTZ4r64zR-M-WSZDfz-JvrbHRF0-MzLo9ZTWupfxXGL-X8njcP2/s1600/img7-29-2013-3.21.11+PM.jpg" style="margin-left: auto; margin-right: auto;" /></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Output Waveform : 8 to 3 Parity Encoder</td></tr>
</tbody></table>
<b><u style="background-color: #fce5cd;"><span style="font-size: large;"><br /></span></u></b>
<b><u style="background-color: #fce5cd;"><span style="font-size: large;">Verilog CODE -</span></u></b><br />
<b><u style="background-color: #fce5cd;"><span style="font-size: large;"><br /></span></u></b>
<b><u style="background-color: #fce5cd;"><span style="font-size: large;"><br /></span></u></b>
<b><u style="background-color: #fce5cd;"><span style="font-size: large;"><br /></span></u></b>
//-----------------------------------------------------------------------------<br />
//<br />
// Title : parity_encoder<br />
// Design : verilog upload 4<br />
// Author : Naresh Singh Dobal<br />
// Company : nsdobal@gmail.com<br />
// Verilog Programs & Exercise with Naresh Singh Dobal<br />
//<br />
//-----------------------------------------------------------------------------<br />
//<br />
// File : Parity Encoder using conditional operator.v<br />
<br />
<br />
module parity_encoder ( din ,dout );<br />
<br />
output [2:0] dout ;<br />
wire [2:0] dout ;<br />
<br />
input [7:0] din ;<br />
wire [7:0] din ;<br />
<br />
assign dout = din[7] ? 0 :<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span> din[6] ? 1 :<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span> din[5] ? 2 :<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span> din[4] ? 3 :<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span> din[3] ? 4 :<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span> din[2] ? 5 :<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span> din[1] ? 6 :<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span> din[0] ? 7 : 1'bzzz ;<br />
<br />
<span style="background-color: #fce5cd;"></span><br />
endmodule<br />
<div>
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</div>
Anonymoushttp://www.blogger.com/profile/03989667403249817442noreply@blogger.com0tag:blogger.com,1999:blog-5787558607075038825.post-83842535996560257592013-07-29T00:19:00.002-07:002013-07-29T00:19:28.969-07:00Design of 8 nibble queue using Behavior Modeling Style (Verilog CODE)-<div dir="ltr" style="text-align: left;" trbidi="on">
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<b><u style="background-color: #fce5cd;"><span style="font-size: large;">Design of 8 nibble queue using Behavior Modeling Style -</span></u></b><br />
<b><u style="background-color: #fce5cd;"><span style="font-size: large;"><br /></span></u></b>
<b><u style="background-color: #fce5cd;"><span style="font-size: large;"><br /></span></u></b>
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEisU_L2X3Ixy-NVowy-KbKwnNZ3eW625UXEKPlsLkmzG7LeScG5fsexqn0gGSZSZaUF2w7mnVfDYjmC44vH81w9dUUX92tqieB_Ih2jWUHKQwCctarNVwVCoov9AzhAcuP1glgBRqgNlzIs/s1600/img7-29-2013-12.20.40+PM.jpg" style="margin-left: auto; margin-right: auto;" /></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Output Waveform : 8 nibble queue Design</td></tr>
</tbody></table>
<b><u style="background-color: #fce5cd;"><span style="font-size: large;"><br /></span></u></b>
<b><u style="background-color: #fce5cd;"><span style="font-size: large;"><br /></span></u></b>
<b><u style="background-color: #fce5cd;"><span style="font-size: large;">Verilog CODE -</span></u></b><br />
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<br />
<br />
//-----------------------------------------------------------------------------<br />
//<br />
// Title : queue_8nibble<br />
// Design : verilog upload 4<br />
// Author : Naresh Singh Dobal<br />
// Company : nsdobal@gmail.com<br />
// Verilog Programs & Exercise with Naresh Singh Dobal<br />
//<br />
//-----------------------------------------------------------------------------<br />
//<br />
// File : 8 nibble queue design using behavior modeling style.v<br />
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<br />
module queue_8nibble ( din ,clk ,push ,pull ,dout );<br />
<br />
output [3:0] dout ;<br />
reg [3:0] dout ;<br />
<br />
input [3:0] din ;<br />
wire [3:0] din ;<br />
input clk ;<br />
wire clk ;<br />
input push ;<br />
wire push ;<br />
input pull ;<br />
wire pull ;<span class="Apple-tab-span" style="white-space: pre;"> </span> <br />
<br />
reg [3:0]queue[0:7];<br />
<br />
integer i;<br />
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initial i = 0;<br />
<br />
always @ (posedge (clk)) begin<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>if (push) begin<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>queue[i] <= din;<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>if (i<7)<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>i <= i +1;<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>end<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>else if (pull) begin<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>dout <= queue[0]; <span class="Apple-tab-span" style="white-space: pre;"> </span><br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>queue[0] <= queue[1];<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>queue[1] <= queue[2];<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>queue[2] <= queue[3];<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>queue[3] <= queue[4];<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>queue[4] <= queue[5];<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>queue[5] <= queue[6];<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>queue[6] <= queue[7];<span class="Apple-tab-span" style="white-space: pre;"> </span><br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>if (i>0)<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>i <= i -1;<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>end<br />
end<br />
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endmodule<br />
<div>
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</div>
Anonymoushttp://www.blogger.com/profile/03989667403249817442noreply@blogger.com0tag:blogger.com,1999:blog-5787558607075038825.post-8915273346969189012013-07-29T00:17:00.000-07:002013-07-29T00:17:30.016-07:00Design of 8 nibble Stack using Behavior Modeling Style (Verilog CODE).<div dir="ltr" style="text-align: left;" trbidi="on">
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<b><u style="background-color: #fce5cd;"><span style="font-size: large;">Design of 8 - nibble STACK using Behavior Modeling Style -</span></u></b><br />
<b><u style="background-color: #fce5cd;"><span style="font-size: large;"><br /></span></u></b>
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<b><u style="background-color: #fce5cd;"><span style="font-size: large;"><br /></span></u></b>
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhlqtLzArMSBcrS8errzeDlb5mLxxSWPrMb5FFo1vmJJQYLAX9RlQTk4hrlu2zuo0cyZX3Gc4CFA1Z7PeZ2WF52gvuoQMw4McTtMYvgMztTWkrbGgB2TFQuBTgoSk2arnTEIvwhEWdYWVdb/s1600/img7-27-2013-1.14.26+PM.jpg" style="margin-left: auto; margin-right: auto;" /></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Output Waveform : 8 ibble STACK Design</td></tr>
</tbody></table>
<b><u style="background-color: #fce5cd;"><span style="font-size: large;"><br /></span></u></b>
<b><u style="background-color: #fce5cd;"><span style="font-size: large;"><br /></span></u></b>
<b><u style="background-color: #fce5cd;"><span style="font-size: large;">Verilog CODE -</span></u></b><br />
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<br />
<br />
//-----------------------------------------------------------------------------<br />
//<br />
// Title : stack_8nibble<br />
// Design : verilog upload 4<br />
// Author : Naresh Singh Dobal<br />
// Company : nsdobal@gmail.com<br />
// Verilog Programs & Exercise with Naresh Singh Dobal<br />
//<br />
//-----------------------------------------------------------------------------<br />
//<br />
// File : Design of 8 nibble stack using behavior modeling style.v<br />
<br />
<br />
module stack_8nibble ( clk ,push ,pull ,din ,dout );<br />
<br />
output [3:0] dout ;<br />
reg [3:0] dout ;<br />
<br />
input clk ;<br />
wire clk ;<br />
input push ;<br />
wire push ;<br />
input pull ;<br />
wire pull ;<br />
input [3:0] din ;<br />
wire [3:0] din ;<br />
<br />
reg [3:0] stack [0:7] ;<br />
<br />
reg [3:0] i;<br />
<br />
initial i = 0;<br />
<br />
always @ (posedge (clk)) begin<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>if (push) begin<span class="Apple-tab-span" style="white-space: pre;"> </span><br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>stack[i] <= din;<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>i <= i + 1;<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>end else if (pull) begin<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>dout <= stack[i];<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>i <= i - 1;<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>end<br />
end<span class="Apple-tab-span" style="white-space: pre;"> </span><br />
<br />
endmodule<br />
<div>
<br /></div>
</div>
Anonymoushttp://www.blogger.com/profile/03989667403249817442noreply@blogger.com0tag:blogger.com,1999:blog-5787558607075038825.post-40672852284954255462013-07-28T23:36:00.002-07:002013-07-28T23:36:50.090-07:00Design of Parallel IN - Serial OUT Shift Register using Behavior Modeling Style (Verilog CODE).<div dir="ltr" style="text-align: left;" trbidi="on">
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<b><u style="background-color: #fce5cd;"><span style="font-size: large;">Design of Parallel In - Serial OUT Shift Register using Behavior Modeling Style -</span></u></b><br />
<b><u style="background-color: #fce5cd;"><span style="font-size: large;"><br /></span></u></b>
<b><u style="background-color: #fce5cd;"><span style="font-size: large;"><br /></span></u></b>
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjS3-NAQW5JBbCYMVFlp0hYO5v8V_htA97xT1B1ogckJIgWFSX49DfATFk8iR2PyMhGU516BpEI3ug5r24Ktx_Tz2CkpdGb43aMIVkHkQd1md9XP4zO3GidbyzpgVlq_YgqQMzby7SGychO/s1600/img7-29-2013-12.01.01+PM.jpg" style="margin-left: auto; margin-right: auto;" /></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Output Waveform : Parallel IN - Serial OUT Shift Register</td></tr>
</tbody></table>
<b><u style="background-color: #fce5cd;"><span style="font-size: large;"><br /></span></u></b>
<b><u style="background-color: #fce5cd;"><span style="font-size: large;"><br /></span></u></b>
<b><u style="background-color: #fce5cd;"><span style="font-size: large;"><br /></span></u></b>
<b><u style="background-color: #fce5cd;"><span style="font-size: large;">Verilog CODE -</span></u></b><br />
<br />
<br />
<br />
//-----------------------------------------------------------------------------<br />
//<br />
// Title : parallel_in_serial_out<br />
// Design : vhdl_upload2<br />
// Author : Naresh Singh Dobal<br />
// Company : nsdobal@gmail.com<br />
// Verilog HDL Programs & Exercise with Naresh Singh Dobal.<br />
//<br />
//-----------------------------------------------------------------------------<br />
//<br />
// File : Parallel IN - Serial OUT Shift Register.v<br />
<br />
<br />
module parallel_in_serial_out ( din ,clk ,reset ,load ,dout );<br />
<br />
output dout ;<br />
reg dout ;<br />
<br />
input [3:0] din ;<br />
wire [3:0] din ;<br />
input clk ;<br />
wire clk ;<br />
input reset ;<br />
wire reset ;<br />
input load ;<br />
wire load ;<br />
<br />
reg [3:0]temp;<br />
<br />
always @ (posedge (clk)) begin<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>if (reset)<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>temp <= 1;<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>else if (load)<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>temp <= din;<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>else begin<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>dout <= temp[3];<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>temp <= {temp[2:0],1'b0};<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>end<br />
end<br />
<br />
endmodule<br />
<div>
<br /></div>
</div>
Anonymoushttp://www.blogger.com/profile/03989667403249817442noreply@blogger.com9tag:blogger.com,1999:blog-5787558607075038825.post-64222411935826031412013-07-28T02:28:00.001-07:002013-07-28T02:28:18.310-07:00FPGA / CPLD Based Project<div dir="ltr" style="text-align: left;" trbidi="on">
<b style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"><span style="font-size: medium;"><span style="background-color: #fce5cd;"><u><br /></u></span></span></b>
<b style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"><span style="font-size: medium;"><span style="background-color: #fce5cd;"><u><br /></u></span></span></b>
<b style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"><span style="font-size: medium;"><span style="background-color: #fce5cd;"><u><br /></u></span></span></b>
<b style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"><span style="font-size: medium;"><span style="background-color: #fce5cd;"><u><br /></u></span></span></b>
<b style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"><span style="font-size: medium;"><span style="background-color: #fce5cd;"><u><br /></u></span></span></b>
<b style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"><span style="font-size: medium;"><span style="background-color: #fce5cd;"><u>FPGA / CPLD Based Project -</u></span></span></b><br style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;" /><b style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"><br /></b><span style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"></span><b style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"><br /></b><span style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"></span><br />
<ul style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;"></ul>
<ol style="color: #222222; font-family: Arial, Verdana; font-size: 14px; line-height: 20px;">
<li><b><a href="http://www.youtube.com/watch?v=vntQJnCAVK4" style="color: #3366cc; outline: none; text-decoration: none;">Full Functional Industrial Digital Clock with Time & Alarm Setting with LCD Interfacing.</a></b></li>
<li><b><a href="http://www.youtube.com/watch?v=FWFpnU6Drok" style="color: #3366cc; outline: none; text-decoration: none;">Interesting 2 Digit Dice Game Project.</a></b></li>
<li><b><a href="http://www.youtube.com/watch?v=6Yc3L8s22kY" style="color: #3366cc; outline: none; text-decoration: none;">Industrial Count Down Timer with Time Setting and Buzzer.</a></b></li>
<li><b><a href="http://www.youtube.com/watch?v=1G5_4Hl3RVw" style="color: #3366cc; outline: none; text-decoration: none;">Two Tokan Display with Direct Restart key and hold feature.</a></b></li>
<li><b>GSM Control Robot with LCD Display (Shows Received Commands). </b></li>
<li><b>Metro Train Prototype System With LCD, Motor and automatic Door and Buzzer Interface.</b></li>
<li><b>GSM Control Home Appliances.</b></li>
<li><b>Wireless RF Controlled Robot With Transmission Power Saving and LCD Display.</b></li>
<li><b><a href="http://www.youtube.com/watch?v=iLma7b_zwaM" style="color: #3366cc; outline: none; text-decoration: none;">RF Controlled robot with lcd display using RF modules</a></b></li>
<li><b>Home aplliances control remotely using RF module with two mode display.</b></li>
<li><b><a href="http://www.youtube.com/watch?v=3pI0DsC5wJE" style="color: #3366cc; outline: none; text-decoration: none;">Multi function stepper motor control (direction_rotations).</a></b></li>
<li><b>Sleep Mode time for any electrical appliances (more than 4 hours of timer).</b></li>
<li><b>Automatic UV light controller for PCB development process.</b></li>
<li><b>Electrical energy saver using home automation.</b></li>
<li><b>Automatic auditorium Management system,</b></li>
<li><b>Physiometer</b></li>
<li><b>Line Following Robot</b></li>
<li><b>Obstacle avoiding robot</b></li>
<li><b>Wall Following robot</b></li>
<li><b>Table anti-falling robot.</b></li>
<li><b><a href="http://www.youtube.com/watch?v=xA-u6sYjw14" style="color: #3366cc; outline: none; text-decoration: none;">Digital Frequency Meter.</a></b></li>
<li><b>Digital Voltmeter</b></li>
<li><b>Wireless RF based car parking monitoring & indicator system.</b></li>
<li><b>Blind walking stick with pre-recorded voice system.</b></li>
<li><b>Temperature controlled automatic fan.</b></li>
<li><b>Intelligent street light controller prototype system.</b></li>
<li><b><a href="http://www.youtube.com/watch?v=Au-hFO6WBZ4" style="color: #3366cc; outline: none; text-decoration: none;">Fastest Finger Detection System.</a></b></li>
<li><b><a href="http://www.youtube.com/watch?v=STdXzocXYSU" style="color: #3366cc; outline: none; text-decoration: none;">Temperature controller with hight and low temperature settings.</a></b></li>
<li><b>Password based door locking system.</b></li>
<li><b>Contactless Technometer.</b></li>
<li><b>Wireless RF Based Object Counter monitoring on veryer belt for industry.</b></li>
<li><b>Wireless RF Home Security System.</b></li>
<li><b>Wireless RF Code Lock lor car/door security.</b></li>
<li><b>Wireless RF Local Positioning system prototype for one vichle.</b></li>
<li><b>Telephone call meter.</b></li>
<li><b>Dsitance monitoring robot with wireless RF Technolgogy.</b></li>
<li><b>Wireless RF based fan speed controller (100 mt range).</b></li>
<li><b>Object Following Robot.</b></li>
<li><b>Wireless Home/Office Security system against theif, fire, gas leakage with autodialar.</b></li>
<li><b>Food Rail.</b></li>
<li><b>Automatic Temperature based CPU fan controller.</b></li>
<li><b>Multi-functional robot with LCD Display.</b></li>
<li><b>Modular Addition Technique (MOD-7).</b></li>
<li><b>Industrial Object Counter with faulty Item detection and controlling.</b></li>
<li><b><a href="http://www.youtube.com/watch?v=K3BnSnispJw" style="color: #3366cc; outline: none; text-decoration: none;">Automatic Garage System with wireless controlled gate and 30 sec. timer.</a></b></li>
<li><b>Automatic Railway Crossing system.</b></li>
<li><b>Full Automatic Water Pump Controlling Device.</b></li>
<li><b>Step Based Stepper Motor controlling.</b></li>
<li><b>Servo Motor Controlling with 1 degree flexibility.</b></li>
<li><b>Prototype of Automatic lift system.</b></li>
<li><b>DTMF based contact number logger system.</b></li>
<li><b><a href="http://www.youtube.com/watch?v=ip7VjLc3OWE" style="color: #3366cc; outline: none; text-decoration: none;">Number System conversion system.</a></b></li>
<li><b>Fire Fighting robot</b></li>
<li><b>1 min. sound message recorder and re-player system.</b></li>
<li><b>Wireless robot control with speed controlling.</b></li>
<li><b>Day Calculater</b></li>
<li><b>GSM Fan speed Controller.</b></li>
<li><b>Digital Controlling of DC motor with wireless RPM measurement.</b></li>
<li><b>Digital Bus prototype system.</b></li>
<li><b>Controlling electric appliances using IR modules.</b></li>
<li><b>Light Following Robot</b></li>
<li><b>Wireless Robot control using IR module</b></li>
<li><b>Fan speed control using IR module</b></li>
<li><b>LPG & CNG gas leackage detector and controller.</b></li>
<li><b>Wireless weather monitoring system.</b></li>
<li><b>Automatic plant irrigator.</b></li>
<li><b>Wireless Pedometer.</b></li>
<li><b>Automatic School Bell.</b></li>
<li><b>GSM based digital code door lock with password change feature.</b></li>
<li><b>Electronic voting machine.</b></li>
<li><b>Prototype of automatic hand washer.</b></li>
<li><b>Clap operated robot.</b></li>
<li><b>Master following robot threw IR sensor.</b></li>
<li><b>LED light chaser with different patterns & continuous key speed control.</b></li>
<li><b><a href="http://www.youtube.com/watch?v=_-9c6stGyig" style="color: #3366cc; outline: none; text-decoration: none;">In/Out Visitor Counter.</a></b></li>
<li><b><a href="http://www.youtube.com/watch?v=XNx81Z53S1A" style="color: #3366cc; outline: none; text-decoration: none;">GSM controlled automatic and password secured car garrage.</a></b></li>
<li><b>32 LED Casino Game with Decreasing running speed.</b></li>
<li><b>GSM Controlled Home security system.</b></li>
<li><b>Wireless dual dc motor speed and direction control using PWM.</b></li>
<li><b>Motor cycle universal gear indicator.</b></li>
<li><b><a href="http://www.youtube.com/watch?v=sORCpOjvxIE" style="color: #3366cc; outline: none; text-decoration: none;">Wireless controlled viewing angle of security camera using two servos.</a></b></li>
<li><b><a href="http://www.youtube.com/watch?v=XjfMGqyiARg" style="color: #3366cc; outline: none; text-decoration: none;">Wireles servo motor controlling with 10 degree ste (+/-) and lcd display.</a></b></li>
<li><b>IR communication between two devices.</b></li>
<li><b><a href="http://www.youtube.com/watch?v=MpMLth95h7M" style="color: #3366cc; outline: none; text-decoration: none;">Industrial Verison of Fastest Finger First ystem.</a></b></li>
<li><b>Fixed Digital Frequency Generator with LCD display up to 50 MHz.</b></li>
<li><b><a href="http://www.youtube.com/watch?v=bwR92TnDWcU" style="color: #3366cc; outline: none; text-decoration: none;">Wireless servo motor controlling with LCD display.</a></b></li>
<li><b> Autonomus path follower with front obstacle detection system.</b></li>
<li><b><a href="http://www.youtube.com/watch?v=v21HubpHgBM" style="color: #3366cc; outline: none; text-decoration: none;">Automatic 180 degree camera motion control for security with speed control.</a></b></li>
<li><b>Password based time bomb.</b></li>
<li><b>Predefined programmed path follower without any line with front obstacle detector.</b></li>
<li><b>User programmable path follower without any line with front obstacle detector.</b></li>
<li><b>Mobile Controlled DC motor control.</b></li>
<li><b>Stepper Motor Control through RF Link.</b></li>
<li><b>Potentiometer based stepper motor control.</b></li>
<li><b>Timer Based Electronics oven and temperature monitoring.</b></li>
<li><b>UART based Digital clock using rs232 protocol.</b></li>
<li><b>UART based Temperature logger using rs232 protocol.</b></li>
<li><b>UART Based count down timer clock with log data recorder.</b></li>
<li><b>UART based type Writer using 6x5 keypad and lcd display.</b></li>
<li><b>Microwave oven with automatic temperature and timer.</b></li>
<li><b>Real Time Direction Finder of Motor.</b></li>
<li><b>Direction and speed Finder of motor.</b></li>
<li><b><a href="http://www.youtube.com/watch?v=qLbYsZBlFvo" style="color: #3366cc; outline: none; text-decoration: none;">Two Tokan Display for Fast Food Centers.</a></b></li>
<li><b>Message Moving Display on 5x28 LED matrix for 12 characters.</b></li>
<li><b>Communication Encoders and Decoders</b></li>
<li><b>Rectangle & circle & Polygen Design using two stepper motor</b></li>
<li><b>Advanced Encryption Technique (128 bit encryption) AES</b></li>
<li><b>Wireless stepper motor speed and direction control</b></li>
<li><b>Automatic washing machine</b></li>
<li><b>Path Follower with front obstacle detection & antifalling robot</b></li>
<li><b><a href="http://www.youtube.com/watch?v=6bpS9sL9ahM" style="color: #3366cc; outline: none; text-decoration: none;">Digital Clock with alarm flexible settings.</a></b></li>
</ol>
</div>
Anonymoushttp://www.blogger.com/profile/03989667403249817442noreply@blogger.com0tag:blogger.com,1999:blog-5787558607075038825.post-51195261074650434352013-07-28T01:00:00.003-07:002013-07-28T01:00:47.516-07:00System Design using Loop Statements (Behavior Modeling Style)<div dir="ltr" style="text-align: left;" trbidi="on">
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<b><u style="background-color: #fce5cd;"><span style="font-size: large;">System Design using LOOP Statements (Behavior Modeling Style) -</span></u></b><br />
<br />
<br />
<b><u style="background-color: #fce5cd;"><span style="font-size: large;"><br /></span></u></b>
<b><u style="background-color: #fce5cd;"><span style="font-size: large;">Loops Statemetns (Behavior Modeling Style) -</span></u></b><br />
<br />
<br />
<ul style="text-align: left;">
<li>FOR Loop.</li>
<li>WHILE Loop.</li>
<li>FOREVER Loop.</li>
<li>REPEAT Loop.</li>
</ul>
<div>
<br /></div>
<div>
<br /></div>
<div>
<br /></div>
<div>
<b><u style="background-color: #fce5cd;"><span style="font-size: large;">FOR Loop Syntax -</span></u></b></div>
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<div>
<b><span style="color: blue;">for </span> ( initilization ; condition ; increment ) <span style="color: blue;">begin</span></b></div>
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<b> </b></div>
<div>
<b> Sequential Statements ;</b></div>
<div>
<b><br /></b></div>
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<b><span style="color: blue;">end</span></b></div>
<div>
<br /></div>
<div>
<br /></div>
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<div>
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<div>
<b><u style="background-color: #fce5cd;"><span style="font-size: large;">While Loops Syntax -</span></u></b></div>
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<br /></div>
<div>
<br /></div>
<div>
<b><span style="color: blue;">while </span> (condition) <span style="color: blue;">begin</span></b></div>
<div>
<b> </b></div>
<div>
<b> Sequential Statements ;</b></div>
<div>
<b><br /></b></div>
<div>
<span style="color: blue;"><b>end</b></span></div>
<div>
<span style="color: blue;"><b><br /></b></span></div>
<div>
<span style="color: blue;"><b><br /></b></span></div>
<div>
<span style="color: blue;"><b><br /></b></span></div>
<div>
<span style="color: blue;"><b><br /></b></span></div>
<div>
<u><b style="background-color: #fce5cd;"><span style="font-size: large;">Forever Loop Syntax -</span></b></u></div>
<div>
<span style="color: blue;"><b><br /></b></span></div>
<div>
<span style="color: blue;"><b><br /></b></span></div>
<div>
<span style="color: blue;"><b>forever begin</b></span></div>
<div>
<span style="color: blue;"><b><br /></b></span></div>
<div>
<b> Sequential Statements ;</b></div>
<div>
<span style="color: blue;"><b><br /></b></span></div>
<div>
<span style="color: blue;"><b>end</b></span></div>
<div>
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<div>
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<div>
<br /></div>
<div>
<br /></div>
<div>
<b><u style="background-color: #fce5cd;"><span style="font-size: large;">Repeat Loop Syntax -</span></u></b></div>
<div>
<br /></div>
<div>
<br /></div>
<div>
<b><span style="color: blue;">repeat</span> (numbers) <span style="color: blue;"> begin</span></b></div>
<div>
<b><br /></b></div>
<div>
<b> Sequential Statements ;</b></div>
<div>
<b><br /></b></div>
<div>
<b><span style="color: blue;">end</span></b></div>
<div>
<b><span style="color: blue;"><br /></span></b></div>
<div>
<b><span style="color: blue;"><br /></span></b></div>
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<b><span style="color: blue;"><br /></span></b></div>
<div>
<b><span style="color: blue;"><br /></span></b></div>
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<b><u style="background-color: #fce5cd;"><span style="font-size: large;">Sample Programs for Loops Statements -</span></u></b></div>
<div>
<br /></div>
<div>
<b><br /></b></div>
<div>
<ul style="text-align: left;">
<li><b><a href="http://verilogbynaresh.blogspot.in/2013/07/design-of-4-bit-adder-using-loops.html">Design of 4 Bit Adder using For Loop (Verilog CODE).</a></b></li>
<li><b><a href="http://verilogbynaresh.blogspot.in/2013/07/design-of-4-bit-subtractor-using-loops.html">Design of 4 Bit Subtractor using For Loop (Verilog CODE).</a></b></li>
<li><b><a href="http://verilogbynaresh.blogspot.in/2013/07/design-of-4-bit-adder-cum-subtractor_28.html">Design of 4 Bit adder/subtractor using For Loop (Verilog CODE).</a></b></li>
</ul>
<div>
<br /></div>
</div>
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Anonymoushttp://www.blogger.com/profile/03989667403249817442noreply@blogger.com0tag:blogger.com,1999:blog-5787558607075038825.post-53604274073799412272013-07-28T00:51:00.001-07:002013-07-28T00:51:14.461-07:00Sample Programs for Basic Systems using Verilog HDL<div dir="ltr" style="text-align: left;" trbidi="on">
<br />
<br />
<br />
<br />
<br />
<br />
<b><u style="background-color: #fce5cd;"><span style="font-size: large;">Sample Programs for Basic Systems using Verilog HDL -</span></u></b><br />
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<br />
<br />
<br />
<ul style="text-align: left;">
<li><b><a href="http://verilogbynaresh.blogspot.in/2013/07/design-of-odd-counter-using-fsm.html">Design of ODD Counter using FSM Technique (Verilog CODE).</a></b></li>
<li><b><a href="http://verilogbynaresh.blogspot.in/2013/07/timer-based-single-way-traffic-light.html">Timer Based Single Way Traffic Light Controller (Verilog CODE).</a></b></li>
<li><b><a href="http://verilogbynaresh.blogspot.in/2013/07/sensor-based-traffic-light-controller.html">Sensor Based Single Way Traffic Light Controller (Verilog CODE).</a></b></li>
<li><b><a href="http://verilogbynaresh.blogspot.in/2013/07/design-of-8-nibble-rom-memory-using.html">Design of 8 Nibble ROM (Memory) using Behavior Modeling (Verilog CODE).</a></b></li>
<li><b><a href="http://verilogbynaresh.blogspot.in/2013/07/design-of-8-nibble-ram-memory-using.html">Design of 8 Nibble RAM (Memory) using Behavior Modeling (Verilog CODE).</a></b></li>
<li><b><a href="http://verilogbynaresh.blogspot.in/2013/07/design-of-first-in-first-out-fifo.html">Design of First IN- First OUT Register using Behavior Model (Verilog Code).</a></b></li>
<li><b>Design of 8 nibble STACK using Behavior Model (Verilog CODE).</b></li>
<li><b><a href="http://verilogbynaresh.blogspot.in/2013/07/design-of-stepper-motor-driver-full.html">Design of Stepper Motor Controller (Full Step) using Behavior Model (Verilog CODE).</a></b></li>
<li><b><a href="http://verilogbynaresh.blogspot.in/2013/07/design-of-stepper-motor-driver-half.html">Design of Stepper Motor Controller (Half Step) using Behavior Model) Verilog CODE.</a></b></li>
</ul>
<br />
<br /></div>
Anonymoushttp://www.blogger.com/profile/03989667403249817442noreply@blogger.com0tag:blogger.com,1999:blog-5787558607075038825.post-41975481991726388112013-07-28T00:44:00.002-07:002013-07-28T00:44:41.686-07:00Design of 4 Bit Adder cum Subtractor using Loops (Behavior Modeling Style) (verilog Code) -<div dir="ltr" style="text-align: left;" trbidi="on">
<br />
<br />
<br />
<br />
<b><u style="background-color: #fce5cd;"><span style="font-size: large;">Design of 4 Bit Adder cum Subtractor using Loops (Behavior Modeling Style) -</span></u></b><br />
<b><u style="background-color: #fce5cd;"><span style="font-size: large;"><br /></span></u></b>
<b><u style="background-color: #fce5cd;"><span style="font-size: large;"><br /></span></u></b>
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiiZDVB0ASCc3vxtc0HSgHYbcQ-9_vTDeKuGHLSksu-RpfYFN1Rl5WNqzgCo6_70dcbo8Ge0BmRKbtYBbdlswo3ihnwd2UrK5E4PGZpYqA_N7v2oFuiLtNZNK6AUMk-r0f-B8lDnNrsRclv/s1600/img7-16-2013-7.37.38+PM.jpg" style="margin-left: auto; margin-right: auto;" /></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Output Waveform : 4 Bit Adder cum Subtractor</td></tr>
</tbody></table>
<b><u style="background-color: #fce5cd;"><span style="font-size: large;"><br /></span></u></b>
<b><u style="background-color: #fce5cd;"><span style="font-size: large;"><br /></span></u></b>
<b><u style="background-color: #fce5cd;"><span style="font-size: large;">Verilog CODE -</span></u></b><br />
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<br />
<br />
//-----------------------------------------------------------------------------<br />
//<br />
// Title : adder_subtractor_4bit<br />
// Design : verilog upload 4<br />
// Author : Naresh Singh Dobal<br />
// Company : nsdobal@gmail.com<br />
// Verilog Programs & Exercise with Naresh Singh Dobal<br />
//<br />
//-----------------------------------------------------------------------------<br />
//<br />
// File : Design of 4 Bit adder cum subtractor.v<br />
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module adder_subtractor_4bit ( a ,b ,sel ,dout );<br />
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output [3:0] dout ;<br />
reg [3:0] dout ;<br />
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input [3:0] a ;<br />
wire [3:0] a ;<br />
input [3:0] b ;<br />
wire [3:0] b ;<br />
input sel ;<br />
wire sel ;<br />
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reg [4:0] s;<br />
wire [3:0] l;<span class="Apple-tab-span" style="white-space: pre;"> </span><br />
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integer i;<br />
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assign l = b ^ {sel,sel,sel,sel};<br />
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always @ (a or b or sel) begin<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>s[0] = sel;<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>for (i=0;i<=3;i=i+1) begin<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>dout[i] = a[i] ^ l[i] ^ s[i];<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>s[i+1] = (a[i] & l[i]) | (l[i] & s[i]) | (s[i] & a[i]);<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>end<br />
end<br />
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endmodule<br />
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Anonymoushttp://www.blogger.com/profile/03989667403249817442noreply@blogger.com0tag:blogger.com,1999:blog-5787558607075038825.post-34213078550295797292013-07-28T00:41:00.001-07:002013-07-28T00:41:24.717-07:00Design of 4 Bit Subtractor using Loops (Behavior Modeling Style) Verilog CODE<div dir="ltr" style="text-align: left;" trbidi="on">
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<b><u style="background-color: #fce5cd;"><span style="font-size: large;">Design of 4 Bit Subtractor using Loops (Behavior Modeling Style) -</span></u></b><br />
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<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjSMV_5XeIjGWdIjSJKekBEF4lDe_UEZb9unUhxXM64ZpfH8pj4tFDFpQelVZZBtGWMt6npVLHw3SF7akvThHhxTnPtBQOmtsNG8YrcKPhyDlu4rh6daPejQ5MAkLHJlIEUtZ9QPdaZHGf9/s1600/img7-16-2013-6.55.03+PM.jpg" style="margin-left: auto; margin-right: auto;" /></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Output Waveform : 4 Bit Subtractor</td></tr>
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<b><u style="background-color: #fce5cd;"><span style="font-size: large;">Verilog CODE-</span></u></b><br />
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//-----------------------------------------------------------------------------<br />
//<br />
// Title : subtractor_4bit<br />
// Design : verilog upload 4<br />
// Author : Naresh Singh Dobal<br />
// Company : nsdobal@gmail.com<br />
// Verilog Programs & Exercise with Naresh Singh Dobal<br />
//<br />
//-----------------------------------------------------------------------------<br />
//<br />
// File : Design of 4 Bit Subtractor using loops.v<br />
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module subtractor_4bit ( a ,b ,diff ,borrow );<br />
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output [3:0] diff ;<br />
reg [3:0] diff ;<br />
output borrow ;<br />
reg borrow ;<br />
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input [3:0] a ;<br />
wire [3:0] a ;<br />
input [3:0] b ;<br />
wire [3:0] b ;<br />
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reg [4:0]s;<br />
wire [3:0]l;<br />
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assign l = ~ b;<br />
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integer i;<br />
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always @ (a or b) begin<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>s[0] = 1;<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>for (i=0;i<=3;i=i+1) begin<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>diff[i] = a[i] ^ l[i] ^ s[i];<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>s[i+1] = (a[i] & l[i]) | (l[i] & s[i]) | (s[i] & a[i]) ;<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>end<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>borrow = s[4];<br />
end<br />
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endmodule<br />
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Anonymoushttp://www.blogger.com/profile/03989667403249817442noreply@blogger.com2